Hi Archit,
On Thu, 7 Jan 2016 11:12:47 +0530
Archit Taneja wrote:
>
>
> On 01/06/2016 05:55 PM, Boris Brezillon wrote:
> > Add basic support for the sil902x RGB -> HDMI bridge.
> > This driver does not support audio output yet.
> >
> > Signed-off-by
On Wed, 6 Jan 2016 10:13:57 -0600
Rob Herring wrote:
> On Wed, Jan 6, 2016 at 9:37 AM, Boris Brezillon
> wrote:
> > On Wed, 6 Jan 2016 09:14:44 -0600
> > Rob Herring wrote:
> >
> >> On Tue, Jan 05, 2016 at 10:55:01AM +0530, Archit Taneja wrote:
> >> &
defining aggregated mtd devices in the DT is not supported, and
since, as I've been told many times ;), DT is supposed to represent the
HW not what we want to do with it, I'm not sure that's such a good idea.
Note that the infrastructure to concatenate several MTD devices
already exis
= <4>;
> + nand-ecc-step-size = <512>;
> + nand-bus-width = <8>;
> +
It's now recommended to define a 'partitions' subnode to store those
partition nodes.
> + #address-cells = <1>;
> + #size-cells = <1>
Hi Sascha,
On Wed, 6 Jan 2016 14:47:36 +0100
Sascha Hauer wrote:
> Hi Boris,
>
> On Wed, Jan 06, 2016 at 12:25:50PM +0100, Boris Brezillon wrote:
> > Add basic support for the sil902x RGB -> HDMI bridge.
> > This driver does not support audio output yet.
> >
>
Hi Rob,
On Wed, 6 Jan 2016 07:19:59 -0600
Rob Herring wrote:
> On Wed, Jan 06, 2016 at 12:25:51PM +0100, Boris Brezillon wrote:
> > Add Sil9022 DT bindings description.
> >
> > Signed-off-by: Boris Brezillon
> > ---
> > .../devicetree/binding
Add basic support for the sil902x RGB -> HDMI bridge.
This driver does not support audio output yet.
Signed-off-by: Boris Brezillon
---
Hello,
This patch is only adding basic support for the sil9022 chip.
As stated in the commit log, there's no audio support, but the
driver also hardcod
Add basic support for the sil902x RGB -> HDMI bridge.
This driver does not support audio output yet.
Signed-off-by: Boris Brezillon
---
Hello,
This patch is only adding basic support for the sil9022 chip.
As stated in the commit log, there's no audio support, but the
driver also hardcod
Add Sil9022 DT bindings description.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/display/bridge/sil902x.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/sil902x.txt
diff --git a/Documentation
by on the previous version, but you seem to
have forgotten it.
Reviewed-by: Boris Brezillon
> ---
> v9 -> v10:
> - Added Rob Herring's Acked-by.
>
> v8 -> v9:
> - Document that partitions are represented as a child node of a NAND chip.
>
> v7 -> v8:
d-off-by: Alex Smith
> Cc: Zubair Lutfullah Kakakhel
> Cc: David Woodhouse
> Cc: Brian Norris
> Cc: Paul Burton
> Cc: linux-...@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-ker...@vger.kernel.org
> Cc: linux-m...@linux-mips.org
> Cc: r...@kernel.org
&
our driver, your NAND
controller can address multiple chips (NAND_DEV_SEL register). Since DT
bindings are supposed to be as stable as possible, I would recommend
separating the NAND controller and NAND chip declaration (as done here
[1] and here [2]).
Best Regards,
Boris
[1]http://lxr.free-elect
<5>;
> + ingenic,nemc-tBP = <10>;
> + ingenic,nemc-tAW = <15>;
> + ingenic,nemc-tSTRV = <100>;
I guess those are encoding controller specific timings. Maybe they
could be automatically deduced from nand_timings information
ubair Lutfullah Kakakhel
> Cc: David Woodhouse
> Cc: Brian Norris
> Cc: linux-...@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-ker...@vger.kernel.org
> Signed-off-by: Harvey Hunt
FWIW:
Reviewed-by: Boris Brezillon
> ---
> v8 -> v9:
> - Docum
estions have been made before I started my
nand_controller/nand_chip separation work, and I think we can get
something way simpler if we switch to a model where the core
implements most of the initialization steps (including parsing of
generic DT properties) and ask the controller to do its specific
initial
On Wed, 11 Nov 2015 16:26:04 -0800
Brian Norris wrote:
> We now stick the device node representing the current MTD (if any) into
> sysfs, so let's make sure we have a reference to it before doing that.
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Brian Norri
properties for a
> +BCH controller.
> +
> +Required BCH properties:
> +- compatible: Should be set to "ingenic,jz4780-bch".
> +- reg: Should specify the BCH controller registers location and length.
> +- clocks: Clock for the BCH controller.
> +
> +Example:
> +
> +bch: bch@134d {
> + compatible = "ingenic,jz4780-bch";
> + reg = <0x134d 0x1>;
> +
> + clocks = <&cgu JZ4780_CLK_BCH>;
> +};
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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= <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x80>;
+ };
+ /* ... */
+
+ };
+ };
+};
Best Regards,
B
; proposals for per-partition ECC handling for NAND, I think.
But do we really care about this case? I mean, if someone is stupid
enough to put different values for two overlapping partitions it
won't work correctly. The only thing we could do is complain loudly
about this mismatch.
For the per-part
ed the ->dev_ready() or ->waitfunc()
fields, and to choose how to implement it he may need to know
which kind of RB handler should be used (this is the case in the sunxi
driver, where the user can either use a GPIO or native R/B pin directly
connected to the controller).
All this makes m
don't think there are multiple gpios for r/b# function.
Because it's supposed to be a generic binding, and some NAND chips
embed several dies, thus exposing several CS and RB pins, hence the
rb-gpios name.
Also, as described here [1], the convention is to name your property
-gpios ev
a clk driver for the internal clk case?
This way you'll be able to use the clk API (including the
clk_get_rate() function) instead of introducing a new way to retrieve a
clk frequency.
Best Regards,
Boris
[1]http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/clock/fixed-clock.txt
oes not add such a big
overhead...
The only thing you have to do is cache a bunch of register values
per-chip and restore/apply them when the chip is selected
(in your ->select_chip() implementation).
Anyway, even if the suggested DT representation is a lie in regards to
your implementation, it'
; actually.
Exactly.
>
> If the HW ECC really doesn't give you valid data+OOB at this point, then
> you might have to re-read with ECC disabled. Of course, that's got a
> performance cost...
As suggested above, if that's possible, reading the OOB area (or a
portio
ct some partitioning schemes
> considered invalid.
>
> Now there is stricter checking above so this can be removed.
Indeed, I was worried about resources deallocation, but this is handle
by the caller, and if nr_parts is zero the master MTD device will
be exposed.
--
Boris Brezill
(*pparts)[i].size = of_read_number(reg + a_cells, s_cells);
>
> @@ -92,15 +116,15 @@ static int parse_ofpart_partitions(struct mtd_info
> *master,
> i++;
> }
>
> - if (!i) {
> - of_node_put(pp);
> - pr_err("No valid p
s in a subnode and patch the ofpart code to parse this subnode
if it is present (see the following patch).
Best Regards,
Boris
--- >8 ---
>From e342860932bda3a6354a0a6e17540db5c85a14e0 Mon Sep 17 00:00:00 2001
From: Boris Brezillon
Date: Thu, 30 Jul 2015 09:44:07 +0200
Subject: [PA
; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flx0_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = &
On Thu, 23 Jul 2015 10:13:11 +0100
Lee Jones wrote:
> On Thu, 23 Jul 2015, Boris Brezillon wrote:
>
> > Hi Lee,
> >
> > On Thu, 23 Jul 2015 08:32:17 +0100
> > Lee Jones wrote:
> >
> > > On Wed, 22 Jul 2015, Cyrille Pitchen wrote:
>
nd usually what we use to attach a node to a specific
driver is the compatible string (this one is specified in the bindings
doc).
Regarding the implementation itself, I would match the child node with
an of_device_id table rather than trying to find a specific substring
in the compatible string, bu
Maximum Duty-Cycle value -- this will normally be
> + 255 (0xff) for an 8 bit PWM device
Why are you introducing another random unit. What is max-duty-cycle
really encoding (I guess it has to do with the precision you're
expecting, but I'm not sure) ?
The PWM frame
Hi Herbert,
On Sun, 21 Jun 2015 16:27:17 +0800
Herbert Xu wrote:
> On Sun, Jun 21, 2015 at 10:24:18AM +0200, Boris Brezillon wrote:
> >
> > Indeed. Here is a patch fixing that.
>
> I think you should just kill COMPILE_TEST instead of adding ARM.
The following
Hi Herbert,
On Sun, 21 Jun 2015 16:27:17 +0800
Herbert Xu wrote:
> On Sun, Jun 21, 2015 at 10:24:18AM +0200, Boris Brezillon wrote:
> >
> > Indeed. Here is a patch fixing that.
>
> I think you should just kill COMPILE_TEST instead of adding ARM.
Okay, I guess I should
Hi Paul,
On Sat, 20 Jun 2015 20:14:08 -0400
Paul Gortmaker wrote:
> On Sat, Jun 20, 2015 at 4:32 PM, Paul Gortmaker
> wrote:
> > On Fri, Jun 19, 2015 at 10:24 AM, Herbert Xu
> > wrote:
> >> On Thu, Jun 18, 2015 at 03:46:16PM +0200, Boris Brezillon wrote:
> >
crypto: marvell/CESA: add MD5 support
crypto: marvell/CESA: add SHA256 support
crypto: marvell/CESA: add support for Kirkwood and Dove SoCs
Boris Brezillon (10):
crypto: mv_cesa: document the clocks property
crypto: mv_cesa: use gen_pool to reserve the SRAM memory region
crypto: mv_c
commit introduce the base infrastructure allowing us to add support
for DMA optimization.
It also includes support for one hash (SHA1) and one cipher (AES)
algorithm, and enable those features on the Armada 370 SoC.
Other algorithms and platforms will be added later on.
Signed-off-by: Boris Brezillon
.
Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/mv_cesa.txt | 24 ++---
drivers/crypto/Kconfig
their crypto engine device
to this driver.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 5 -
drivers/crypto/mv_cesa.c | 4 +++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree
Add support for DES operations.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 150
3 files changed, 154 insertions
Add CESA IP description for all the missing armada SoCs (XP, 375 and 38x).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index 9c43cd7e..af590bf
From: Arnaud Ebalard
Add support for MD5 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 172 +-
3 files changed
From: Arnaud Ebalard
Add the Kirkwood and Dove SoC descriptions, and control the allhwsupport
module parameter to avoid probing the CESA IP when the old CESA driver is
enabled (unless it is explicitly requested to do so).
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
explicitly requested to do
so).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 42 +++---
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index a05b5cb..8e5ea72
From: Arnaud Ebalard
Add support for SHA256 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 159 ++
3 files
per platform basis.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/marvell/Makefile | 2 +-
drivers/crypto/marvell/cesa.c | 68 +++
drivers/crypto/marvell/cesa.h | 229 ++
drivers/crypto
is stable/secure enough.
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index af590bf..a05b5cb 100644
--- a/drivers/crypto/marvell/cesa.c
+++ b/drivers/crypto
Add DT bindings documentation for the new marvell-cesa driver.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/marvell-cesa.txt| 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/marvell-cesa.txt
diff
From: Arnaud Ebalard
Add support for Triple-DES operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 147
3
On Dove platforms, the crypto engine requires a clock. Document this
clocks property in the mv_cesa bindings doc.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
n be used at a time. The active function is selected though
> the Flexcom Mode Register.
For the whole series,
Acked-by: Boris Brezillon
>
> Cyrille Pitchen (2):
> mfd: devicetree: add bindings for Atmel Flexcom
> mfd: flexcom: add a driver for Atmel Flexible Serial Communicatio
On Thu, 18 Jun 2015 10:48:03 +0100
Russell King - ARM Linux wrote:
> On Thu, Jun 18, 2015 at 11:33:24AM +0200, Boris Brezillon wrote:
> > Hi Russel,
> >
> > On Thu, 18 Jun 2015 10:04:00 +0100
> > Russell King - ARM Linux wrote:
> >
> > > On Wed, Ju
Hi Russel,
On Thu, 18 Jun 2015 10:04:00 +0100
Russell King - ARM Linux wrote:
> On Wed, Jun 17, 2015 at 05:50:01PM +0800, Herbert Xu wrote:
> > On Wed, Jun 17, 2015 at 09:45:33AM +0200, Boris Brezillon wrote:
> > >
> > > + ret = dma_map_sg(cesa_dev->
Hi Herbert,
On Wed, 17 Jun 2015 09:45:34 +0200
Boris Brezillon wrote:
> Add support for DES operations.
The addition of DES support seems controversial. At first I thought it
would be good to support all the algorithms supported by the CESA
engine, but I think I'll drop it in
On Wed, 17 Jun 2015 17:34:02 +0200
Boris Brezillon wrote:
> On Wed, 17 Jun 2015 23:08:08 +0800
> Herbert Xu wrote:
>
> > On Wed, Jun 17, 2015 at 03:32:02PM +0200, Boris Brezillon wrote:
> > >
> > > Hi Herbert,
> > >
> > > I send you this
On Wed, 17 Jun 2015 23:08:08 +0800
Herbert Xu wrote:
> On Wed, Jun 17, 2015 at 03:32:02PM +0200, Boris Brezillon wrote:
> >
> > Hi Herbert,
> >
> > I send you this patch alone so that you can verify I'm now properly
> > manipulating the SG list. Once I ha
per platform basis.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
Hi Herbert,
I send you this patch alone so that you can verify I'm now properly
manipulating the SG list. Once I have your confirmation I'll send
the whole series again and annoy all the people in C
On Wed, 17 Jun 2015 17:50:01 +0800
Herbert Xu wrote:
> On Wed, Jun 17, 2015 at 09:45:33AM +0200, Boris Brezillon wrote:
> >
> > + ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
> > +DMA_TO_DEVICE);
> > + if (
commit introduce the base infrastructure allowing us to add support
for DMA optimization.
It also includes support for one hash (SHA1) and one cipher (AES)
algorithm, and enable those features on the Armada 370 SoC.
Other algorithms and platforms will be added later on.
Signed-off-by: Boris Brezillon
Add support for DES operations.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 150
3 files changed, 154 insertions
From: Arnaud Ebalard
Add support for MD5 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 172 +-
3 files changed
From: Arnaud Ebalard
Add support for SHA256 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 159 ++
3 files
Add DT bindings documentation for the new marvell-cesa driver.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/marvell-cesa.txt| 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/marvell-cesa.txt
diff
From: Arnaud Ebalard
Add the Kirkwood and Dove SoC descriptions, and control the allhwsupport
module parameter to avoid probing the CESA IP when the old CESA driver is
enabled (unless it is explicitly requested to do so).
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
explicitly requested to do
so).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 42 +++---
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index a05b5cb..8e5ea72
Add CESA IP description for all the missing armada SoCs (XP, 375 and 38x).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index 9c43cd7e..af590bf
From: Arnaud Ebalard
Add support for Triple-DES operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 147
3
.
Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/mv_cesa.txt | 24 ++---
drivers/crypto/Kconfig
is stable/secure enough.
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index af590bf..a05b5cb 100644
--- a/drivers/crypto/marvell/cesa.c
+++ b/drivers/crypto
their crypto engine device
to this driver.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 5 -
drivers/crypto/mv_cesa.c | 4 +++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree
On Dove platforms, the crypto engine requires a clock. Document this
clocks property in the mv_cesa bindings doc.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
per platform basis.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/marvell/Makefile | 2 +-
drivers/crypto/marvell/cesa.c | 68 +++
drivers/crypto/marvell/cesa.h | 229 ++
drivers/crypto
tion issues
- (suggested by Andrew) added DT changes to the series
Arnaud Ebalard (4):
crypto: marvell/CESA: add Triple-DES support
crypto: marvell/CESA: add MD5 support
crypto: marvell/CESA: add SHA256 support
crypto: marvell/CESA: add support for Kirkwood and Dove SoCs
Boris Brezillon (10
On Wed, 17 Jun 2015 15:18:29 +0800
Herbert Xu wrote:
> On Wed, Jun 17, 2015 at 09:15:03AM +0200, Boris Brezillon wrote:
> >
> > Anyway, now I'm doing the following test:
> >
> > if (creq->src_nents && !ret)
> > return -ENOMEM;
>
> Best
On Wed, 17 Jun 2015 13:58:24 +0800
Herbert Xu wrote:
> On Tue, Jun 16, 2015 at 11:58:58AM +0200, Boris Brezillon wrote:
> >
> > +config CRYPTO_DEV_MARVELL_CESA
> > + tristate "New Marvell's Cryptographic Engine driver"
> > + depends on (PLAT_ORION
On Wed, 17 Jun 2015 13:56:33 +0800
Herbert Xu wrote:
> On Wed, Jun 17, 2015 at 01:05:27PM +0800, Herbert Xu wrote:
> > On Tue, Jun 16, 2015 at 11:58:59AM +0200, Boris Brezillon wrote:
> > >
> > > + ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
&g
From: Arnaud Ebalard
Add support for Triple-DES operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 147
3
From: Arnaud Ebalard
Add support for MD5 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 172 +-
3 files changed
commit introduce the base infrastructure allowing us to add support
for DMA optimization.
It also includes support for one hash (SHA1) and one cipher (AES)
algorithm, and enable those features on the Armada 370 SoC.
Other algorithms and platforms will be added later on.
Signed-off-by: Boris Brezillon
Add support for DES operations.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 150
3 files changed, 154 insertions
Add CESA IP description for all the missing armada SoCs (XP, 375 and 38x).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index 9c43cd7e..af590bf
explicitly requested to do
so).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 42 +++---
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index a05b5cb..8e5ea72
From: Arnaud Ebalard
Add the Kirkwood and Dove SoC descriptions, and control the allhwsupport
module parameter to avoid probing the CESA IP when the old CESA driver is
enabled (unless it is explicitly requested to do so).
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
per platform basis.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/marvell/Makefile | 2 +-
drivers/crypto/marvell/cesa.c | 68 +++
drivers/crypto/marvell/cesa.h | 229 ++
drivers/crypto
is stable/secure enough.
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index af590bf..a05b5cb 100644
--- a/drivers/crypto/marvell/cesa.c
+++ b/drivers/crypto
Add DT bindings documentation for the new marvell-cesa driver.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/marvell-cesa.txt| 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/marvell-cesa.txt
diff
From: Arnaud Ebalard
Add support for SHA256 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 159 ++
3 files
.
Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/mv_cesa.txt | 24 ++---
drivers/crypto/Kconfig
their crypto engine device
to this driver.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 5 -
drivers/crypto/mv_cesa.c | 4 +++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree
On Dove platforms, the crypto engine requires a clock. Document this
clocks property in the mv_cesa bindings doc.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
A: add Triple-DES support
crypto: marvell/CESA: add MD5 support
crypto: marvell/CESA: add SHA256 support
crypto: marvell/CESA: add support for Kirkwood and Dove SoCs
Boris Brezillon (10):
crypto: mv_cesa: document the clocks property
crypto: mv_cesa: use gen_pool to reserve the SRAM memory re
))
> + mr = FX_MR_USART;
> + else if (!strcmp(mode, "spi"))
> + mr = FX_MR_SPI;
> + else if (!strcmp(mode, "twi") || !strcmp(mode, "i2c"))
> + mr = FX_MR_TWI;
> + else
> + return -EINVA
5d2-flexcom";
reg = <0xf8034000 0x800>;
clocks = <&flx0_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8034000 0x800>;
atmel,flexcom-mode = "spi";
usart@200 {
reg = <0x200 0x100>;
On Mon, 15 Jun 2015 17:37:54 +0800
Herbert Xu wrote:
> On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote:
> >
> > +static inline int mv_cesa_sg_count(struct scatterlist *sg, int nbytes)
> > +{
> > + int nents = 0;
> > +
> > + whi
On Mon, 15 Jun 2015 17:48:27 +0800
Herbert Xu wrote:
> On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote:
> >
> > +static void mv_cesa_dequeue_req_unlocked(struct mv_cesa_engine *engine)
> > +{
> > + struct crypto_async_request *req;
>
On Mon, 15 Jun 2015 17:54:21 +0800
Herbert Xu wrote:
> On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote:
> >
> > +static int mv_cesa_cbc_aes_op(struct ablkcipher_request *req,
> > + struct mv_cesa_op_ctx *tmpl)
> > +{
> &g
On Mon, 15 Jun 2015 17:59:44 +0800
Herbert Xu wrote:
> On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote:
> > +struct ahash_alg mv_ahmac_sha1_alg = {
> > + .init = mv_cesa_ahmac_sha1_init,
> > + .update = mv_cesa_ahash_update,
> > + .
Hi Herbert,
On Mon, 15 Jun 2015 18:09:20 +0800
Herbert Xu wrote:
> On Fri, Jun 12, 2015 at 09:15:57AM +0200, Boris Brezillon wrote:
> >
> > + ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
> > +DMA_TO_DEVICE);
> > + if
their crypto engine device
to this driver.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 5 -
drivers/crypto/mv_cesa.c | 4 +++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree
From: Arnaud Ebalard
Add support for SHA256 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 157 ++
3 files
Add CESA IP description for all the missing armada SoCs (XP, 375 and 38x).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index e4dfee0..087370e
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