On Tue, 8 Dec 2015 08:53:54 +0100
Maxime Ripard wrote:
> Look, we all agreed on a solution that raised all objections, but
> yours.
>
> I'm going to take Jens patch.
OK. Good luck for the next SoCs!
--
Ken ar c'hentaƱ | ** Breizh ha Linux atav! **
Jef | h
Hi Jean-Francois,
On Tue, Dec 08, 2015 at 07:42:26AM +0100, Jean-Francois Moine wrote:
> On Mon, 7 Dec 2015 08:31:02 -0600
> Rob Herring wrote:
>
> > On Sun, Dec 06, 2015 at 10:04:12AM +0100, Jean-Francois Moine wrote:
> > > The H3 has a clock gate definition similar to the other Allwinner SoCs,
On Mon, 7 Dec 2015 08:31:02 -0600
Rob Herring wrote:
> On Sun, Dec 06, 2015 at 10:04:12AM +0100, Jean-Francois Moine wrote:
> > The H3 has a clock gate definition similar to the other Allwinner SoCs,
> > but with a different parent clock for each single gate.
> >
> > Adding the names of the pare
On Sun, Dec 06, 2015 at 10:04:12AM +0100, Jean-Francois Moine wrote:
> The H3 has a clock gate definition similar to the other Allwinner SoCs,
> but with a different parent clock for each single gate.
>
> Adding the names of the parent clocks in both the source and output clocks
> permits the use
The H3 has a clock gate definition similar to the other Allwinner SoCs,
but with a different parent clock for each single gate.
Adding the names of the parent clocks in both the source and output clocks
permits the use of the simple-gates driver to define the bus gates
of all known Allwinner SoCs.