On 18/12/15 13:33, Geert Uytterhoeven wrote:
Hi Dirk,
On Fri, Dec 18, 2015 at 12:56 PM, Dirk Behme wrote:
On 18.12.2015 12:03, Geert Uytterhoeven wrote:
On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme wrote:
From: Geert Uytterhoeven
Add device nodes for the L2 caches, and link the CPU node
Hi Dirk,
On Fri, Dec 18, 2015 at 12:56 PM, Dirk Behme wrote:
> On 18.12.2015 12:03, Geert Uytterhoeven wrote:
>> On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme wrote:
>>> From: Geert Uytterhoeven
>>>
>>> Add device nodes for the L2 caches, and link the CPU node to its L2
>>> cache node.
>>>
>>> Th
On 18.12.2015 12:03, Geert Uytterhoeven wrote:
Hi Dirk,
On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme wrote:
From: Geert Uytterhoeven
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB
Hi Dirk,
On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme wrote:
> From: Geert Uytterhoeven
>
> Add device nodes for the L2 caches, and link the CPU node to its L2
> cache node.
>
> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
> 128 KiB x 16 ways).
>
> The L2 cache for the C
From: Geert Uytterhoeven
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Signed
