On Friday 21 November 2014 23:28:38 Jassi Brar wrote:
> On 21 November 2014 22:45, Arnd Bergmann wrote:
> > On Friday 21 November 2014 22:06:51 Jassi Brar wrote:
>
> >> >> Only MB86S70_CRG11_UNGPRT is marked to mean one special (non-maskable)
> >> >> port on the controller, which the clock driver
On 21 November 2014 22:45, Arnd Bergmann wrote:
> On Friday 21 November 2014 22:06:51 Jassi Brar wrote:
>> >> Only MB86S70_CRG11_UNGPRT is marked to mean one special (non-maskable)
>> >> port on the controller, which the clock driver does make use of.
>> >
>> > Is this the actual port number that
On Friday 21 November 2014 22:06:51 Jassi Brar wrote:
> On 21 November 2014 20:04, Arnd Bergmann wrote:
> > On Friday 21 November 2014 18:52:47 Jassi Brar wrote:
> >> On 21 November 2014 18:33, Arnd Bergmann wrote:
> >> > On Thursday 20 November 2014 20:36:15 Vincent Yang wrote:
> >> >> +#define
On 21 November 2014 20:04, Arnd Bergmann wrote:
> On Friday 21 November 2014 18:52:47 Jassi Brar wrote:
>> On 21 November 2014 18:33, Arnd Bergmann wrote:
>> > On Thursday 20 November 2014 20:36:15 Vincent Yang wrote:
>> >> +#define __DTS_MB86S70_CLK_H
>> >> +
>> >> +#define MB86S70_CRG11_ALW
On Friday 21 November 2014 18:52:47 Jassi Brar wrote:
> On 21 November 2014 18:33, Arnd Bergmann wrote:
> > On Thursday 20 November 2014 20:36:15 Vincent Yang wrote:
> >> +#define __DTS_MB86S70_CLK_H
> >> +
> >> +#define MB86S70_CRG11_ALW 0
> >> +#define MB86S70_CRG11_DDR3 1
> >> +#define
On 21 November 2014 18:33, Arnd Bergmann wrote:
> On Thursday 20 November 2014 20:36:15 Vincent Yang wrote:
>> +#define __DTS_MB86S70_CLK_H
>> +
>> +#define MB86S70_CRG11_ALW 0
>> +#define MB86S70_CRG11_DDR3 1
>> +#define MB86S70_CRG11_MAIN 2
>> +#define MB86S70_CRG11_CA15 3
>> +#
On Thursday 20 November 2014 20:36:15 Vincent Yang wrote:
> +#define __DTS_MB86S70_CLK_H
> +
> +#define MB86S70_CRG11_ALW 0
> +#define MB86S70_CRG11_DDR3 1
> +#define MB86S70_CRG11_MAIN 2
> +#define MB86S70_CRG11_CA15 3
> +#define MB86S70_CRG11_HDMI 4
> +#define MB86S70_CRG11_D
The CRG11 clock controller is managed by remote f/w.
This driver simply maps Linux CLK ops onto mailbox api.
Signed-off-by: Andy Green
Signed-off-by: Jassi Brar
Signed-off-by: Vincent Yang
Signed-off-by: Tetsuya Nuriya
---
.../bindings/clock/fujitsu,mb86s70-clk.txt | 34 ++
drivers/