On Wed, Mar 25, 2015 at 2:23 AM, Ralf Baechle wrote:
> On Thu, Dec 25, 2014 at 09:49:10AM -0800, Kevin Cernekee wrote:
>
>> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
>> the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
>> may cause parts of the DMA
On Thu, Dec 25, 2014 at 09:49:10AM -0800, Kevin Cernekee wrote:
> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
> the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
> may cause parts of the DMA buffer to be prefetched into the RAC. To
> avoid possible c
BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC. To
avoid possible coherency problems, flush the RAC upon DMA completion.
Signed-off-by: Kev
