Re: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache

2014-02-18 Thread Andrew Lunn
> > +Required properties: > > +- compatible : Should be either "marvell,ferocean-cache" or > > + "marvell,kirkwood-cache". > > + > > +Optional properties: > > +- wt-override: If present then L2 is forced to Write through mode > > +- reg: Address of the L2 cache control register. Ma

Re: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache

2014-02-17 Thread Jason Cooper
On Sat, Feb 15, 2014 at 11:20:08AM +0100, Andrew Lunn wrote: > Instantiate the L2 cache from DT. Indicate in DT where the cache > control register is and if write through should be made. > > Signed-off-by: Andrew Lunn > cc: devicetree@vger.kernel.org > --- > v2: > Change compatible strings to fol

Re: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache

2014-02-15 Thread Nicolas Pitre
On Sat, 15 Feb 2014, Arnd Bergmann wrote: > On Saturday 15 February 2014, Andrew Lunn wrote: > > None of the _defconfig's ever turn on > > CACHE_FEROCEON_L2_WRITETHROUGH. I also did a quick google and could > > not find any usage of it. > > > > So i see two options: > > > > 1) Remove the wr-over

Re: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache

2014-02-15 Thread Arnd Bergmann
On Saturday 15 February 2014, Andrew Lunn wrote: > None of the _defconfig's ever turn on > CACHE_FEROCEON_L2_WRITETHROUGH. I also did a quick google and could > not find any usage of it. > > So i see two options: > > 1) Remove the wr-override from the DT binding and use > CACHE_FEROCEON_L2_WRITET

Re: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache

2014-02-15 Thread Andrew Lunn
On Sat, Feb 15, 2014 at 02:23:23PM +0100, Arnd Bergmann wrote: > On Saturday 15 February 2014 11:20:08 Andrew Lunn wrote: > > Instantiate the L2 cache from DT. Indicate in DT where the cache > > control register is and if write through should be made. > > > > Signed-off-by: Andrew Lunn > > cc: de

Re: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache

2014-02-15 Thread Arnd Bergmann
On Saturday 15 February 2014 11:20:08 Andrew Lunn wrote: > Instantiate the L2 cache from DT. Indicate in DT where the cache > control register is and if write through should be made. > > Signed-off-by: Andrew Lunn > cc: devicetree@vger.kernel.org > I guess this answers part of my question for p

[PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache

2014-02-15 Thread Andrew Lunn
Instantiate the L2 cache from DT. Indicate in DT where the cache control register is and if write through should be made. Signed-off-by: Andrew Lunn cc: devicetree@vger.kernel.org --- v2: Change compatible strings to follow l2x0 convention Only expect register for kirkwood-cache. Default to write