On Tue, Dec 1, 2015 at 5:24 PM, Carlo Caione wrote:
> From: Carlo Caione
>
> In Meson SoCs we have 8 independent GPIO interrupts that can be programmed to
> use any of the GPIOs in the chip as interrupt source.
>
> These GPIOs are managed by GIC but they can be conditioned (and enabled) by
> som
From: Carlo Caione
In Meson SoCs we have 8 independent GPIO interrupts that can be programmed to
use any of the GPIOs in the chip as interrupt source.
These GPIOs are managed by GIC but they can be conditioned (and enabled) by
some registers external to the GIC.
GPIOs |--[mux1 or mux2]--[polari
