Hi Rob,
I think we should first agreed on the DT binding and let's not worry
about APEI. Then, whether we have one file or multiple file. Again,
the HW consist of:
1. One top level interrupt and status registers
>
> For these registers, are there ECC specific functions her
On Thu, Apr 30, 2015 at 09:57:46AM -0700, Loc Ho wrote:
> I had read all the emails interaction. Yes I can write a single EDAC
> driver. But I actually have multiple instances and single instance of
> the same IP's. For example, I have 4 DDR controllers, 4 CPU domains,
> one L3 and one SoC. If you
On Thursday 30 April 2015 11:41:34 Borislav Petkov wrote:
> But if those three vendors went and created an EDAC module each for
> their system, it would be a lot of repeated copy'pasting and bloat.
>
> Now, the other dimension doesn't look better either:
>
> xgene_edac_mc
> xgene_edac_mc-v2
> xge
On Wed, Apr 29, 2015 at 4:56 PM, Loc Ho wrote:
> Hi,
>
>>> > Similar comments for the rest. I would define memory controller
>>> > bindings and EDAC driver, then worry about the rest.
>>>
>>> Okay.. As comment in following emails, I will break up the driver into
>>> multiple drivers and focus only
On Wed, Apr 29, 2015 at 02:56:25PM -0700, Loc Ho wrote:
> Hi,
>
> >> > Similar comments for the rest. I would define memory controller
> >> > bindings and EDAC driver, then worry about the rest.
> >>
> >> Okay.. As comment in following emails, I will break up the driver into
> >> multiple drivers
Hi,
>> > Similar comments for the rest. I would define memory controller
>> > bindings and EDAC driver, then worry about the rest.
>>
>> Okay.. As comment in following emails, I will break up the driver into
>> multiple drivers and focus only on the memory controller driver first.
>
> Please no mu
This patch adds documentation for the APM X-Gene SoC EDAC DTS binding.
Signed-off-by: Feng Kan
Signed-off-by: Loc Ho
---
.../devicetree/bindings/edac/apm-xgene-edac.txt| 107
1 files changed, 107 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetre
