[PATCH v13 4/4] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4d68184d3f76..02986055fdbc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11484,6 +11484,12 @@ L: l

[PATCH v13 3/4] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml' contains 'mediatek' as a valid vendor string. Some nodes in the device tree are using an invalid vendor string vfor 'mtk' instead. Fix all of them in dts file. Update also ralink mt7621 related code to properly match new string

[PATCH v13 2/4] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos ---

[PATCH v13 1/4] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or s

[PATCH v13 0/4] MIPS: ralink: add CPU clock detection and clock driver for MT7621

did not wanted to make assumptions of a clock plan for the platform that time. It seems that now he has a better idea of how the clocks are dispossed for this SoC so he share code[1] where some frequencies and clock parents for the gates are coded from a real mediatek private clock plan.

[driver-core:driver-core-testing] BUILD SUCCESS 312723a0b34d6d110aa4427a982536bb36ab8471

allyesconfig mips allmodconfig powerpc allyesconfig powerpc allmodconfig powerpc allnoconfig i386 randconfig-a006-20210409 i386 randconfig-a003

[staging:staging-testing] BUILD SUCCESS d55c46f360279862d62dc03b8de3104e2786f026

allyesconfig mips allmodconfig powerpc allyesconfig powerpc allmodconfig powerpc allnoconfig i386 randconfig-a006-20210409 i386 randconfig-a003-20210409 i386

[staging:staging-next] BUILD SUCCESS e7442ffe1cc5d89d101a99ff78eb68edb1961e30

i386 randconfig-a006-20210409 i386 randconfig-a003-20210409 i386 randconfig-a001-20210409 i386 randconfig-a004-20210409 i386 randconfig-a002-20210409 i386 randconfig-a005-20210409 x86_64

Re: [PATCH v10 8/9] dt-bindings: add documentation of xilinx clocking wizard

Quoting Michal Simek (2021-04-08 03:40:29) > > > On 4/8/21 12:26 PM, Shubhrajyoti Datta wrote: > > On Sun, Mar 7, 2021 at 1:50 AM Rob Herring wrote: > >> > >> On Wed, Feb 24, 2021 at 06:40:40PM +0530, Shubhrajyoti Datta wrote: > >>> Add the devicetree binding for the xilinx clocking wizard. > >>

[PATCH v12 4/4] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..ecad5d972122 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L: l

[PATCH v12 1/4] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or s

[PATCH v12 2/4] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos ---

[PATCH v12 0/4] MIPS: ralink: add CPU clock detection and clock driver for MT7621

This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers

[PATCH v12 3/4] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml' contains 'mediatek' as a valid vendor string. Some nodes in the device tree are using an invalid vendor string vfor 'mtk' instead. Fix all of them in dts file. Update also ralink mt7621 related code to properly match new string

Re: [PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

Quoting Sergio Paracuellos (2021-04-09 11:34:35) > On Fri, Apr 9, 2021 at 8:14 PM Stephen Boyd wrote: > > > > Quoting Sergio Paracuellos (2021-03-08 21:22:23) > > > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile > > > new file mode 100644 > > > index ..cf6f92163

Re: [PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

Hi, On Fri, Apr 9, 2021 at 8:14 PM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2021-03-08 21:22:23) > > diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig > > new file mode 100644 > > index ..3e3f5cb9ad88 > > --- /dev/null > > +++ b/drivers/clk/ralink/Kconfig

Re: [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Quoting Sergio Paracuellos (2021-03-23 01:13:22) > On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos > wrote: > > > > Changes in v11: > > - Collect Rob's Reviewed-by in bindings documentation patch. > > - Fix MAINTAINERS patch using file 'mediatek,mt7621-sysc.yaml' > >for documentation bindi

Re: [PATCH v11 2/6] dt: bindings: add mt7621-sysc device tree binding documentation

Quoting Sergio Paracuellos (2021-03-08 21:22:22) > Adds device tree binding documentation for clocks in the > MT7621 SOC. > > Reviewed-by: Rob Herring > Signed-off-by: Sergio Paracuellos > --- Applied to clk-next ___ devel mailing list de...@linuxdriv

Re: [PATCH v11 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Quoting Sergio Paracuellos (2021-03-08 21:22:21) > Adds dt binding header for 'mediatek,mt7621-clk' clocks. > > Acked-by: Rob Herring > Signed-off-by: Sergio Paracuellos > --- Applied to clk-next ___ devel mailing list de...@linuxdriverproject.org htt

Re: [PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

Quoting Sergio Paracuellos (2021-03-08 21:22:23) > diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig > new file mode 100644 > index ..3e3f5cb9ad88 > --- /dev/null > +++ b/drivers/clk/ralink/Kconfig > @@ -0,0 +1,15 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +

Re: [PATCH 1/1] drm/bridge: anx7625: send DPCD command to downstream

Hey Xin, On Fri, 9 Apr 2021 at 07:35, Xin Ji wrote: > > Send DPCD command to downstream before anx7625 power down, > tell downstream into standby mode. > > Signed-off-by: Xin Ji > --- > drivers/gpu/drm/bridge/analogix/anx7625.c | 75 +++ > 1 file changed, 75 insertions(+) >