Le 29/11/2021 à 21:13, Adam Ford a écrit :
On Wed, Apr 7, 2021 at 2:37 AM Benjamin Gaignard
wrote:
Introducing the G2 hevc video decoder requires modifications of the bindings to
allow
one node per VPU.
VPUs share one hardware control block which is provided as a phandle on
a syscon.
Each no
On Wed, Apr 7, 2021 at 2:37 AM Benjamin Gaignard
wrote:
>
> Introducing the G2 hevc video decoder requires modifications of the bindings
> to allow
> one node per VPU.
>
> VPUs share one hardware control block which is provided as a phandle on
> a syscon.
> Each node has now one reg and one inter
Introducing the G2 hevc video decoder requires modifications of the bindings to
allow
one node per VPU.
VPUs share one hardware control block which is provided as a phandle on
a syscon.
Each node has now one reg and one interrupt.
Add a compatible for G2 hardware block: nxp,imx8mq-vpu-g2.
To be
