https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61948
Bug ID: 61948 Summary: [ARM] [4.9 regression] ICE with DImode shift by 1 bit (in copyprop_hardreg_forward_1) Product: gcc Version: 4.9.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: cbaylis at gcc dot gnu.org Reporter: cbaylis at gcc dot gnu.org Target: arm-unknown-linux-gnueabihf Created attachment 33202 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=33202&action=edit Original test case, needs -std=c++11 Originally reported at: https://bugs.linaro.org/show_bug.cgi?id=176 The lshrdi3_neon,ashrdi3_neon,ashldi3_neon patterns can call gen_arm_<shift>di3_1bit without checking that the register allocation constraints of the resulting insn are satisfied. This results in an ICE: Simplified test case: ------<======== long long f (long long *c) { long long t = c[0]; /* force t into [r1,r2] */ asm ("nop" : : : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "memory"); return t >> 1; } =======>------- $ arm-unknown-linux-gnueabihf-gcc -O2 -mfpu=neon -mthumb -c t.c t.c: In function âfâ: t.c:8:1: error: insn does not satisfy its constraints: } ^ (insn 18 7 14 2 (parallel [ (set (reg/i:DI 0 r0) (ashiftrt:DI (reg/v:DI 1 r1 [orig:110 t ] [110]) (const_int 1 [0x1]))) (clobber (reg:CC 100 cc)) ]) t.c:8 131 {arm_ashrdi3_1bit} (expr_list:REG_DEAD (reg:SI 2 r2) (expr_list:REG_UNUSED (reg:CC 100 cc) (nil)))) t.c:8:1: internal compiler error: in copyprop_hardreg_forward_1, at regcprop.c:775