[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983 --- Comment #12 from GCC Commits --- The releases/gcc-15 branch has been updated by Xi Ruoyao : https://gcc.gnu.org/g:21a87ad785fe1e7c6504c3cf7984e74fe5a5067a commit r15-10213-g21a87ad785fe1e7c6504c3cf7984e74fe5a5067a Author: Xi Ruoyao Date: Tue Jul 8 14:39:11 2025 +0800 lra: Reallow reloading user hard registers if the insn is not asm [PR 120983] The PR 87600 fix has disallowed reloading user hard registers to resolve earlyclobber-induced conflict. However before reload, recog completely ignores the constraints of insns, so the RTL passes may produce insns where some user hard registers violate an earlyclobber. Then we'll get an ICE without reloading them, like what we are recently encountering in LoongArch test suite. IIUC "recog does not look at constraints until reload" has been a well-established rule in GCC for years and I don't have enough skill to challange it. So reallow reloading user hard registers (but still disallow doing so for asm) to fix the ICE. gcc/ChangeLog: PR rtl-optimization/120983 * lra-constraints.cc (process_alt_operands): Allow reloading user hard registers unless the insn is an asm. (cherry picked from commit e6d3c88e7bb07f94308074f9751e4384a191e022)
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983 --- Comment #11 from GCC Commits --- The releases/gcc-15 branch has been updated by Xi Ruoyao : https://gcc.gnu.org/g:06f43dfbbf314bbe6d0b905fc8780e525ef6e72a commit r15-10212-g06f43dfbbf314bbe6d0b905fc8780e525ef6e72a Author: Xi Ruoyao Date: Tue Jul 8 14:07:21 2025 +0800 testsuite: Enable the PR 87600 tests for LoongArch I'm going to refine a part of the PR 87600 fix which seems triggering PR 120983 that LoongArch is particularly suffering. Enable the PR 87600 tests so I'll not regress PR 87600. gcc/testsuite/ChangeLog: PR rtl-optimization/87600 PR rtl-optimization/120983 * gcc.dg/pr87600.h [__loongarch__]: Define REG0 and REG1. * gcc.dg/pr87600-1.c (dg-do): Add loongarch. * gcc.dg/pr87600-2.c (dg-do): Likewise. (cherry picked from commit 651845ceaae26a1b2c03f215e16e7e711dcea2cc)
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983 --- Comment #10 from Xi Ruoyao --- The issue is exploited by PR120242 fix that we've backported to 15, thus I'll backport the fix to 15 as well to unbreak the test suite.
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983 --- Comment #9 from GCC Commits --- The master branch has been updated by Xi Ruoyao : https://gcc.gnu.org/g:e6d3c88e7bb07f94308074f9751e4384a191e022 commit r16-2215-ge6d3c88e7bb07f94308074f9751e4384a191e022 Author: Xi Ruoyao Date: Tue Jul 8 14:39:11 2025 +0800 lra: Reallow reloading user hard registers if the insn is not asm [PR 120983] The PR 87600 fix has disallowed reloading user hard registers to resolve earlyclobber-induced conflict. However before reload, recog completely ignores the constraints of insns, so the RTL passes may produce insns where some user hard registers violate an earlyclobber. Then we'll get an ICE without reloading them, like what we are recently encountering in LoongArch test suite. IIUC "recog does not look at constraints until reload" has been a well-established rule in GCC for years and I don't have enough skill to challange it. So reallow reloading user hard registers (but still disallow doing so for asm) to fix the ICE. gcc/ChangeLog: PR rtl-optimization/120983 * lra-constraints.cc (process_alt_operands): Allow reloading user hard registers unless the insn is an asm.
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983 --- Comment #8 from GCC Commits --- The master branch has been updated by Xi Ruoyao : https://gcc.gnu.org/g:651845ceaae26a1b2c03f215e16e7e711dcea2cc commit r16-2214-g651845ceaae26a1b2c03f215e16e7e711dcea2cc Author: Xi Ruoyao Date: Tue Jul 8 14:07:21 2025 +0800 testsuite: Enable the PR 87600 tests for LoongArch I'm going to refine a part of the PR 87600 fix which seems triggering PR 120983 that LoongArch is particularly suffering. Enable the PR 87600 tests so I'll not regress PR 87600. gcc/testsuite/ChangeLog: PR rtl-optimization/87600 PR rtl-optimization/120983 * gcc.dg/pr87600.h [__loongarch__]: Define REG0 and REG1. * gcc.dg/pr87600-1.c (dg-do): Add loongarch. * gcc.dg/pr87600-2.c (dg-do): Likewise.
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983 --- Comment #7 from Xi Ruoyao --- https://gcc.gnu.org/pipermail/gcc-patches/2025-July/689000.html
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983
--- Comment #6 from Xi Ruoyao ---
(In reply to Andrew Pinski from comment #4)
> Oh look:
> /* Both the earlyclobber operand and conflicting operand
>cannot both be user defined hard registers. */
> if (HARD_REGISTER_P (operand_reg[i])
> && REG_USERVAR_P (operand_reg[i])
> && operand_reg[j] != NULL_RTX
> && HARD_REGISTER_P (operand_reg[j])
> && REG_USERVAR_P (operand_reg[j]))
> {
> /* For asm, let curr_insn_transform diagnose it. */
> if (INSN_CODE (curr_insn) < 0)
> return false;
> fatal_insn ("unable to generate reloads for "
> "impossible constraints:", curr_insn);
> }
>
>
> Which dates to PR 87600.
Yup, the change was to detect broken inline-asm. But I don't think it should
happen w/o inline-asm.
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983
--- Comment #5 from Andrew Pinski ---
gcc.target/loongarch/bitwise-shift-reassoc-clobber.c:
```
/* { dg-do run } */
/* { dg-options "-O2" } */
register long x asm ("s0");
#define TEST(x) (int)(((x & 0x114) << 3) + x)
[[gnu::noipa]] void
test (void)
{
x = TEST (x);
}
int
main (void)
{
x = 0x;
test ();
if (x != TEST (0x))
__builtin_trap ();
}
```
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983
Andrew Pinski changed:
What|Removed |Added
See Also||https://gcc.gnu.org/bugzill
||a/show_bug.cgi?id=87600
--- Comment #4 from Andrew Pinski ---
Oh look:
/* Both the earlyclobber operand and conflicting operand
cannot both be user defined hard registers. */
if (HARD_REGISTER_P (operand_reg[i])
&& REG_USERVAR_P (operand_reg[i])
&& operand_reg[j] != NULL_RTX
&& HARD_REGISTER_P (operand_reg[j])
&& REG_USERVAR_P (operand_reg[j]))
{
/* For asm, let curr_insn_transform diagnose it. */
if (INSN_CODE (curr_insn) < 0)
return false;
fatal_insn ("unable to generate reloads for "
"impossible constraints:", curr_insn);
}
Which dates to PR 87600.
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983 --- Comment #3 from Segher Boessenkool --- Please attach a testcase, and how to compile the code (-O2 etc.). Oh, and fill in the target field :-)
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983 Andrew Pinski changed: What|Removed |Added Keywords||ra --- Comment #2 from Andrew Pinski --- (In reply to Andrew Pinski from comment #1) > So the problem is before reload only the predicates are used and not the > constraints. The early clobbered is never looked at. > > I wonder why IRA could not generate a reload here though since it could push > (reg:SI 23 $r23 [ x ]) into its own register for the last operand ... Sorry LRA and not IRA.
[Bug rtl-optimization/120983] recog violates earlyclobber with user-defined hard register before reload (causing ICE on gcc.target/loongarch/bitwise-shift-reassoc-clobber.c)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120983 --- Comment #1 from Andrew Pinski --- So the problem is before reload only the predicates are used and not the constraints. The early clobbered is never looked at. I wonder why IRA could not generate a reload here though since it could push (reg:SI 23 $r23 [ x ]) into its own register for the last operand ...
