[Bug target/117818] [13/14/15/16 regression] vec_add incorrectly generates vadduwm for vector char const inputs.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117818 Richard Biener changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed||2026-02-16 Ever confirmed|0 |1 --- Comment #14 from Richard Biener --- I assume confirmed at least.
[Bug target/117818] [13/14/15/16 regression] vec_add incorrectly generates vadduwm for vector char const inputs.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117818 --- Comment #13 from Segher Boessenkool --- BTWQ, vsl and vsr always were (and still are) implemented just like the vslv and vsrv instructions. But it is only defined (in the arch) what it does when all lanes hold the same number.
[Bug target/117818] [13/14/15/16 regression] vec_add incorrectly generates vadduwm for vector char const inputs.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117818 --- Comment #12 from Segher Boessenkool --- Hrm, yeah, the ISA says bits 57..63 of VRB. That seems wrong, 121..127 is more logical. Let me test what existing hardware does.
[Bug target/117818] [13/14/15/16 regression] vec_add incorrectly generates vadduwm for vector char const inputs.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117818 --- Comment #11 from Steven Munroe --- (In reply to Segher Boessenkool from comment #10) > Btw, from power10 on (arch 3.1 and later) vslq (and vsrq) are preferred :-) Noted. PVECLIB will generate these for #if defined(_ARCH_PWR10) https://munroesj52.github.io/vec__int128__ppc_8h.html#a070fe972995f3954362835f5b72e5ff6 https://munroesj52.github.io/vec__int128__ppc_8h.html#a0edd172a5656b842d6586c5078284942 But the same problems exist generating a shift constant to bits[57:63] as for bits [121:127]. Also the PVIPR seems to require the shift count in [121:127] and generates an xxswapd to put the shift count into [57:63] for vslq/vsrq.
[Bug target/117818] [13/14/15/16 regression] vec_add incorrectly generates vadduwm for vector char const inputs.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117818 --- Comment #10 from Segher Boessenkool --- Btw, from power10 on (arch 3.1 and later) vslq (and vsrq) are preferred :-)
[Bug target/117818] [13/14/15/16 regression] vec_add incorrectly generates vadduwm for vector char const inputs.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117818 Richard Biener changed: What|Removed |Added Target Milestone|12.5|13.5 --- Comment #9 from Richard Biener --- GCC 12 branch is being closed.
