https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120368
--- Comment #1 from GCC Commits ---
The master branch has been updated by Jeff Law :
https://gcc.gnu.org/g:8459c546197dc9178d250994db021b36405f1bd6
commit r16-807-g8459c546197dc9178d250994db021b36405f1bd6
Author: Jeff Law
Date: Wed May 21 14:15:23 2025 -0600
[RISC-V][PR target/120368] Fix 32bit shift on rv64
So a followup to last week's bugfix. In last week's change we we stopped
using
define_insn_and_split to rewrite instructions. That change was done to
avoid
dropping a masking instruction out of the RTL.
As a result the pattern(s) were changed into simple define_insns, which is
good. One of them uses the GPR iterator since it's supposed to work for
both
32bit and 64bit shifts on rv64.
But we failed to emit the right opcode for a 32bit shift on rv64.
Thankfully
the fix is trivial. If the mode is anything but word_mode, then we must be
doing a 32-bit shift on rv64, ie the various "w" shift instructions.
It's run through my tester. Just waiting on the upstream CI system to spin
it.
PR target/120368
gcc/
* config/riscv/riscv.md (shift with masked shift count): Fix
opcode when generating an SImode shift on rv64.
gcc/testsuite/
* gcc.target/riscv/pr120368.c: New test.
