[Bug target/120550] [16 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

2025-06-22 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550

--- Comment #6 from Jeffrey A. Law  ---
So this is an ext-dce bug, it just isn't obvious.

ext-dce removes the extension in this insn:

(insn 26 24 29 3 (set (reg:DI 141 [ pretmp_16 ])
(zero_extend:DI (subreg:QI (reg:DI 160) 0))) "j.c":8:5 126
{*zero_extendqidi2_internal}
 (expr_list:REG_DEAD (reg:DI 160) 
(expr_list:REG_EQUAL (zero_extend:DI (mem/c:QI (symbol_ref:DI ("u")
[flags 0x86]  ) [0 u+0 S1 A8]))
(nil

I've traced the values around the CFG and the removal is valid.  But there's a
REG_EQUAL note that gets left around.  So after ext-dce we have:

(insn 26 24 29 3 (set (reg:DI 141 [ pretmp_16 ])
(reg:DI 160)) "j.c":8:5 277 {*movdi_64bit}
 (expr_list:REG_DEAD (reg:DI 160)
(expr_list:REG_EQUAL (zero_extend:DI (mem/c:QI (symbol_ref:DI ("u")
[flags 0x86]  ) [0 u+0 S1 A8]))
(nil


That's the bug.  Combine later kicks in and sees the REG_EQUAL note and adjust
the nonzero bits for (reg 141) in the expected way, but they don't accurately
reflect  the value in (reg 141).  Combine later uses the incorrect nonzero_bits
 and eliminates a different (and necessary) extension.

The fix is simple.  When ext-dce makes a change it can just wipe the REG_EQUAL
note.  We could try and be selective about the notes we remove, but I doubt
it's worth the effort and analysis to be selective.

[Bug target/120550] [16 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

2025-06-06 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550

--- Comment #5 from Jeffrey A. Law  ---
Initial analysis is that ext-dce is fine at least as far as the RTL is
concerned.   Will need to look at combine next.

[Bug target/120550] [16 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

2025-06-06 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550

Jeffrey A. Law  changed:

   What|Removed |Added

   Assignee|unassigned at gcc dot gnu.org  |law at gcc dot gnu.org
 Status|NEW |ASSIGNED

--- Comment #4 from Jeffrey A. Law  ---
Landed on the initial introduction of ext-dce.  Which makes sense if you look
at the two values.  -10 and 246 :-)

Anyway, mine.

[Bug target/120550] [16 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

2025-06-06 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550

--- Comment #3 from Jeffrey A. Law  ---
I suspect the bisection landing on the inliner heuristic change is a bit of a
red herring.  Forcing that first function to be static inline and I can see
this well back in the gcc15  cycle.

[Bug target/120550] [16 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

2025-06-06 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550

Jeffrey A. Law  changed:

   What|Removed |Added

   Last reconfirmed||2025-06-06
 Ever confirmed|0   |1
 Status|UNCONFIRMED |NEW

[Bug target/120550] [16 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

2025-06-04 Thread ewlu at rivosinc dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550

--- Comment #2 from Edwin Lu  ---
(In reply to Andrew Pinski from comment #1)
> Created attachment 61581 [details]
> Might be miscompiled before r16-372
> 
> Can you re-bisect using this testcase? This changes your main into a new
> function which is noinline and calls the new function from main.  This
> basically makes  what r16-372 is doing for main now.

Just tried compiling that testcase with my daily upstream build
(r16-1095-gf8251b4fce2) and wasn't able to produce the miscompile

[Bug target/120550] [16 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

2025-06-04 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550

--- Comment #1 from Andrew Pinski  ---
Created attachment 61581
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=61581&action=edit
Might be miscompiled before r16-372

Can you re-bisect using this testcase? This changes your main into a new
function which is noinline and calls the new function from main.  This
basically makes  what r16-372 is doing for main now.

[Bug target/120550] [16 Regression] RISC-V: Miscompile at -O3 since r16-372-g064cac730f8

2025-06-04 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120550

Andrew Pinski  changed:

   What|Removed |Added

   Target Milestone|--- |16.0
   Keywords||wrong-code
 CC||pinskia at gcc dot gnu.org