[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:e2ba7f34a993ede9400f0b6263445ca3f8c37f3f

commit e2ba7f34a993ede9400f0b6263445ca3f8c37f3f
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 906b7322f72f..8b57c649e5e8 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:b1f931aa2a47953b6fd28941ea5479d2cc005296

commit b1f931aa2a47953b6fd28941ea5479d2cc005296
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 906b7322f72f..8b57c649e5e8 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:c73aa7492260b7e4ebcc686b169b665bbd7557d5

commit c73aa7492260b7e4ebcc686b169b665bbd7557d5
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 906b7322f72f..8b57c649e5e8 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:1eb6c4f220c5b2cc2fb476ee9269aa4e5bd99a2d

commit 1eb6c4f220c5b2cc2fb476ee9269aa4e5bd99a2d
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 906b7322f72f..8b57c649e5e8 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:c49e6dca7136b8fbcc201dd528ef32538c997514

commit c49e6dca7136b8fbcc201dd528ef32538c997514
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 73381ae85c09..ee1571ccd05a 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f11124f1fb8925ec5448eabb0547628a12bae834

commit f11124f1fb8925ec5448eabb0547628a12bae834
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 69f2a1ece534..ce1633c72dee 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:d81f703fad520a77a04e80dd757863ac5431eaf9

commit d81f703fad520a77a04e80dd757863ac5431eaf9
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 69f2a1ece534..ce1633c72dee 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:b86b8dc70d54702694917ede31221402ed8ccff3

commit b86b8dc70d54702694917ede31221402ed8ccff3
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 69f2a1ece534..ce1633c72dee 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:17f6b67746829ce2c4b9887fc245ad8225ea6a74

commit 17f6b67746829ce2c4b9887fc245ad8225ea6a74
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 69f2a1ece534..ce1633c72dee 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:09f1fddc57b496abc27eb1a3f0cea96d0e22e388

commit 09f1fddc57b496abc27eb1a3f0cea96d0e22e388
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc|  2 +-
 .../gcc.target/riscv/rvv/autovec/pr120356.c| 26 ++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 69f2a1ece534..ce1633c72dee 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
new file mode 100644
index ..2913f04e4c83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target rvv_zvl256b_ok } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O2" 
} */
+
+unsigned char a = 5;
+long long c[18];
+
+static void d ()
+{
+  for (short i = 0; i < 60; i += 65413)
+for (char j = 0; j < 18; j++)
+  {
+   for (char k = 0; k < 18; k++)
+ a *= 143;
+   for (char k = 0; k < 6; k++)
+ for (char l = 0; l < 18; l++)
+   c[l] = 0;
+  }
+}
+
+int main ()
+{
+  d ();
+  if (a + c[0] != 69)
+__builtin_abort ();
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:218279a4653032325cbe13c98f8ea38a5d36

commit 218279a4653032325cbe13c98f8ea38a5d36
Author: Alexey Merzlyakov 
Date:   Wed Jul 2 11:29:00 2025 -0600

[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns 
[PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

PR target/120356

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

(cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3)

Diff:
---
 gcc/config/riscv/riscv-v.cc|  2 +-
 .../gcc.target/riscv/rvv/autovec/pr120356.c| 26 ++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 69f2a1ece534..ce1633c72dee 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx 
target, rtx src,
  shifted_vid = gen_reg_rtx (mode);
  rtx shift = gen_int_mode (1, Xmode);
  rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
   shift_ops);
}
   else
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
new file mode 100644
index ..2913f04e4c83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target rvv_zvl256b_ok } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O2" 
} */
+
+unsigned char a = 5;
+long long c[18];
+
+static void d ()
+{
+  for (short i = 0; i < 60; i += 65413)
+for (char j = 0; j < 18; j++)
+  {
+   for (char k = 0; k < 18; k++)
+ a *= 143;
+   for (char k = 0; k < 6; k++)
+ for (char l = 0; l < 18; l++)
+   c[l] = 0;
+  }
+}
+
+int main ()
+{
+  d ();
+  if (a + c[0] != 69)
+__builtin_abort ();
+}