[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:ebfad14f2e403f70cc3bd64040ad8ff69ed7a6ad
commit ebfad14f2e403f70cc3bd64040ad8ff69ed7a6ad
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index bf6197916f91..f00f5dc1b4b2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9670,17 +9670,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:bf2957e239da288eb8de80cc8b83a0d0f723f28c
commit bf2957e239da288eb8de80cc8b83a0d0f723f28c
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index bf6197916f91..f00f5dc1b4b2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9670,17 +9670,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:272c570be0d25b3f0f8930ecb8011e8ffdc2e00b
commit 272c570be0d25b3f0f8930ecb8011e8ffdc2e00b
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0194a4ff2f98..2daf2e48ab79 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9669,17 +9669,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:578cf938dc796c9b2981f878d69b7bc58752c47e
commit 578cf938dc796c9b2981f878d69b7bc58752c47e
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0194a4ff2f98..2daf2e48ab79 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9669,17 +9669,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:b7a7d1fb83ed34a9494a48f5b4a2d1513e85f04e
commit b7a7d1fb83ed34a9494a48f5b4a2d1513e85f04e
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8afa6a322fb6..a7ad01b35bb2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9669,17 +9669,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:33847ab70d3f4dee352ce14d1effc57d0d788e56
commit 33847ab70d3f4dee352ce14d1effc57d0d788e56
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8afa6a322fb6..a7ad01b35bb2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9669,17 +9669,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:d751483109fbb4e195691baedb9e5e350228bfe6
commit d751483109fbb4e195691baedb9e5e350228bfe6
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ab7d9e13f523..c644c2b622a4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9668,17 +9668,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:73ffb70740155644a98594760f2ec3f49c2044dd
commit 73ffb70740155644a98594760f2ec3f49c2044dd
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ab7d9e13f523..c644c2b622a4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9668,17 +9668,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:3051776747d0083817823cda18e3a475a6dc04d5
commit 3051776747d0083817823cda18e3a475a6dc04d5
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 10e0f4adbdcf..064c12c49f3a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9659,17 +9659,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:6021cda2942c9db4e404ed1be26f80a4ec6d7473
commit 6021cda2942c9db4e404ed1be26f80a4ec6d7473
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 10e0f4adbdcf..064c12c49f3a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9659,17 +9659,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix
https://gcc.gnu.org/g:f7d0410edf094d607da120f958c3d0b47d006e2c
commit f7d0410edf094d607da120f958c3d0b47d006e2c
Author: Jeff Law
Date: Sun May 4 08:28:56 2025 -0600
[to-be-committed][RISC-V] Adjust testcases and finish register move costing
fix
The recent adjustment to more correctly cost register moves tripped a few
testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked
because the register move costing was broken. So I've reverted the scan-asm
part of those to a prior state for two of those tests. The other was only
failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable
-mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed those
while I was in there.
Note this may have an impact on some of your work Pan. I haven't followed
the
changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change are
addressed (there's still one for rv32 I'll look at shortly).
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
(cherry picked from commit 005424e3337a3234f95755e57ee41c061b6e4185)
Diff:
---
gcc/config/riscv/riscv.cc | 8
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 4 +---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c| 2 +-
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 10e0f4adbdcf..064c12c49f3a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9659,17 +9659,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c3140578..38966fefad5d 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c3..f0d9c80d16f2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e23784480..81b240eac577 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36ac..150cfd7fc058 100644
--
