[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:46274ece3f2a8e29895686ddd3755a8ef4a242e6

commit 46274ece3f2a8e29895686ddd3755a8ef4a242e6
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:267b826eb7500a8b954462a747f06de23de9b564

commit 267b826eb7500a8b954462a747f06de23de9b564
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:4079e20ff4bc2675ee9c586be208a46a974a940e

commit 4079e20ff4bc2675ee9c586be208a46a974a940e
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:3e087425fba41ed087cdc8de5e04f5bd2f7b1a30

commit 3e087425fba41ed087cdc8de5e04f5bd2f7b1a30
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:97e8a2b92d31971cfa7a893f17dc542eb6b43413

commit 97e8a2b92d31971cfa7a893f17dc542eb6b43413
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:69d67f108494760f781b0e0ba93ba0af00d4c04a

commit 69d67f108494760f781b0e0ba93ba0af00d4c04a
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:670347187ac7a973395d4bdb964533d32bebf6ff

commit 670347187ac7a973395d4bdb964533d32bebf6ff
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:0bddf83335ee4476bff2f5c9c46da812689553b5

commit 0bddf83335ee4476bff2f5c9c46da812689553b5
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:eea8d508e9da0d699268b9341ae3558bb5480c4b

commit eea8d508e9da0d699268b9341ae3558bb5480c4b
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:bfd52bc2926bfebfbb1b9a9fa94de6685e0a40d3

commit bfd52bc2926bfebfbb1b9a9fa94de6685e0a40d3
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:2e800ed614cc8596c462576cddb0afa47114a62c

commit 2e800ed614cc8596c462576cddb0afa47114a62c
Author: yulong 
Date:   Tue Apr 29 21:12:03 2025 +0800

RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

This commit adds testcases for Xsfvcp.

Co-Authored by: Jiawei Chen 
Co-Authored by: Shihua Liao 
Co-Authored by: Yixuan Chen 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test.

(cherry picked from commit cc8b8c0b69200ab816a2626e29d91ac995f7438f)

Diff:
---
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c   |  88 +
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c   | 132 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c   | 107 
 .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c   | 138 +
 4 files changed, 465 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
new file mode 100644
index ..7667e56a4c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_v_fv_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fv_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t 
vl) {
+return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) {
+__riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t 
fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_v_fvv_se_u16m1:
+** ...
+** vsetivli\s+zero+,0+,e16+,m1,ta,ma+
+** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, 
float16_t fs1, size_t vl) {
+return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** vsetivli\s+zero+,0+,e32+,m8,ta,ma+
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl);
+}
+
+
+/*
+** test_sf_vc_fvw_se_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, 
size_t vl) {
+__riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
new file mode 100644
index ..5528cc52ac76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sifive_vector.h"
+
+
+/*
+** test_sf_vc_v_i_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_v_i_se_u16m4:
+** ...
+** vsetivli\s+zero+,0+,e16+,m4,ta,ma+
+** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+
+** ...
+*/
+vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) {
+return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl);
+}
+
+/*
+** test_sf_vc_i_se_u16mf4:
+** ...
+** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+
+** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+
+** ...
+*/
+void test_sf_vc_i_se_u16mf4(size_t vl) {
+__riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl);
+}
+
+/*
+** test_sf_vc_v_iv_u32m2:
+** ...
+** vsetivli\s+zero+,0+,e32+,m2,ta,ma+
+** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+