[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2026-01-29 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:03a48c10a043fa1520fea30e1a5edc016ba1dfa5

commit 03a48c10a043fa1520fea30e1a5edc016ba1dfa5
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2026-01-16 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:f954c166bd5d8bc8286fa8f76d5748ef916f1dd5

commit f954c166bd5d8bc8286fa8f76d5748ef916f1dd5
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2025-11-07 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:d575be6c60124aecafdde73b5c257e2643f067c9

commit d575be6c60124aecafdde73b5c257e2643f067c9
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2025-11-01 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:4d7e1e83df3f592297dc91ec00965186954c4cd9

commit 4d7e1e83df3f592297dc91ec00965186954c4cd9
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2025-10-18 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:0468f670f841d1b6f29de4a94d879c36348c10b5

commit 0468f670f841d1b6f29de4a94d879c36348c10b5
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2025-09-13 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:c2b32dbf9b5465e006e28f657d464fc34968832c

commit c2b32dbf9b5465e006e28f657d464fc34968832c
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2025-09-06 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:362e07433bcaeb5ef7a8748ad185e9bf2d4e372d

commit 362e07433bcaeb5ef7a8748ad185e9bf2d4e372d
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2025-08-25 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:989006f9ebf5d7f532bcf546246fe8d1a7182345

commit 989006f9ebf5d7f532bcf546246fe8d1a7182345
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2025-07-23 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:63d4c1427cca40fafc1bb99d010e3441e64f3131

commit 63d4c1427cca40fafc1bb99d010e3441e64f3131
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2025-07-05 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:b13bb6a4bc41cf07220974bf2594a873afe81fd1

commit b13bb6a4bc41cf07220974bf2594a873afe81fd1
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2025-05-19 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:4935cb10803cc28b9f3aa07023c60d9a7da7a7b0

commit 4935cb10803cc28b9f3aa07023c60d9a7da7a7b0
Author: Pan Li 
Date:   Sun May 18 20:09:05 2025 +0800

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR 
cost 2

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
for vrsub with GR2VR cost 2.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.

Signed-off-by: Pan Li 
(cherry picked from commit d1697f3d685ac9df6136eefc305b5f1297087fbe)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0e5ad322aa5f..ce1b40fd1740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
index b46b74a0887f..7326ded06f0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4);
 
 /* { dg-final { scan-assembler {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
index 13e64d7752b6..7b8b63dd3cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY)
 DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY)
+DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 1f58daaad38f..f440b7075dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16)
+DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler {vsub.vx} } } */
+/* { dg-final { scan-assembler {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
index 2249cb242fe8..c36c5cb64165 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c
@@ -6,6 +6,8 @@
 
 DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8);
 
 /* { dg-final { scan-assembler {vadd.