The Ubuntu gEDA packages are from last year, but they seem to be the
only option. They segfault on page closes for me, and even more often
for a friend. Anybody know why? Are there newer packages available
somewhere?
Thanks,
Matt
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On 10/10/06, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
John Luciani wrote:
> TP + pad size in metric + hole size in metric + height in metric.
TP it is.
How about a single-wire connector such as a .25 faston blade soldered to
the pcb? E.G. Keystone 4966. Thanks.
I would do CON__Keyston
John Luciani wrote:
TP + pad size in metric + hole size in metric + height in metric.
TP it is.
How about a single-wire connector such as a .25 faston blade soldered to
the pcb? E.G. Keystone 4966. Thanks.
Pt
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geda-
On 10/10/06, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
Hi,
I've reviewed the naming conventions sheet, and other sources, but
haven't figured out what to call a single-wire terminal.
I've been calling them something like:
TERM__wire_awg22.fp
Is there a more common name being used? What i
Hi,
I've reviewed the naming conventions sheet, and other sources, but
haven't figured out what to call a single-wire terminal.
I've been calling them something like:
TERM__wire_awg22.fp
Is there a more common name being used? What is it?
Phil
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> I compiled a fresh checkout from CVS, and I tried to load the above
> file into pcb. It took about 10 minutes to load the file, with 100%
> CPU load (CPU is 1300MHz AMD). After it, I realised that all of the
> lines on the component side was joining polygons. I use GTK -
> HID. Should I try expo
Dear all,
I compiled a fresh checkout from CVS, and I tried to load the above file into
pcb. It took about 10 minutes to load the file, with 100% CPU load (CPU is
1300MHz AMD). After it, I realised that all of the lines on the component side
was joining polygons. I use GTK - HID. Should I try
Em Ter 10 Out 2006 09:52, John Luciani escreveu:
> On 10/10/06, Stefan Salewski <[EMAIL PROTECTED]> wrote:
> > My questions:
> > What is the right way to generate the outline for the board
> > producer?
My vendor asks for a 10 mils line around the board.
IN THEORY he cuts the board exactly in the
Stefan,
A quick way to get results is to manually "draw" the board outline on an
empty layer you rename "outline":
This is inelegant, but quick error-free. It requires absolutely no
programming. If "outline" doesn't sound like a good name to your
vendor, you can easily change it.
Layer(7
> Someone more familiar with PCB will be able to tell you if the
> gerbers produced without any components will line up correctly with
> the copy with components (I don't know what PCB takes as the gerber
> origin).
PCB uses an absolute origin for all gerbers, they should all line up
just fine.
Outlines should be drawn with lines on their own "outline"[*] layer.
It should be in its own layer group. Most fabs want 10 mil lines, but
they all seem to use the centerline of the lines as the actual
outline.
The CVS version of pcb has a patch that omits the pins and vias from
the gerber and p
> I have seen this in PCB too. PCB doesn't yet support "mechanical" layers
> such as used for board outlines or cutouts. As a result, if you use any
> through hole parts (or vias), a pad (or via) is placed on every layer's
> gerber output.
>
This too is fixed in the latest CVS code. Also the auto
> I see, you used polygons.
> Make sure, the fab can deal with negative gerber layers.
The new (CVS) version always creates all positive-only gerber files. This
should increase the number of fabs that are happy with pcb's gerber files.
There are 5 styles of thermals available, all of which a
> Well, I think there is something wrong with my outline file
> (board.group2.gbr from http://www.ssalewski.de/board.tar.gz). I
> created a new layer called outline and have drawn only the
> outline-rectangle into this layer. So board.group2.gbr should
> contain only this rectangle. But viewin
Kai-Martin Knaak wrote:
> The separate outline gerber file was fine with Basista.
>
Well, I think there is something wrong with my outline file
(board.group2.gbr from http://www.ssalewski.de/board.tar.gz). I
created a new layer called outline and have drawn only the
outline-rectangle into this
On Tue, 10 Oct 2006 14:04:02 +0200, Stefan Salewski wrote:
> Should I rename the gerber files? (I think name of
> board.group0.gbr should be board.front.gbr, this name was used
> in pcb documentation)
I use a ascript to rename the files and the layer name definitions within
the gerbers. PCB fab
On 10/10/06, Stefan Salewski <[EMAIL PROTECTED]> wrote:
My questions:
What is the right way to generate the outline for the board
producer?
This depends on the manufacturer. I use PCB Express and they request a
1mil copper
line on the top layer. I usually add this line after I complete the lay
Hello,
I have finished my first board using gEDA and will now sent
gerber files to my board manufacturer. I will send data to
www.bilex-lp.com, because they are cheap and accepting gerber
files. (They seem to have only a homepage in german language)
The last two steps i have to do is to create
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