On 3/19/07, Karel Kulhavy <[EMAIL PROTECTED]> wrote:
http://wiki.emqbit.com/free-ecb-at91
Hi Karel (you forgot to say hello).
The licence is GPL and you are stating that the design is free,
but it actually isn't. If anyone takes these files and distributes
them further, he is violating the G
Dan McMahill wrote:
how should PCB behave with a hierarchical
schematic?
by default for each cell to be an entity that
you can grab and move around. The ability to visually toggle all
hierarchical instances between the contents and a box is fairly useful.
[jg]As in Cadence. To save on r
al davis wrote:
* Finally, how should PCB behave with a hierarchical
schematic?
Right click on a symbol, select "go inside", and another drawing
opens up showing what's inside. gschem also should act this
way.
I think what you want is by default for each cell to be an entity that
you c
Mikael W. Bertelsen wrote:
Hi all!
I tried out the gEDA package and I am very impressed! My thanks to all
who contributed to this project!
I created a layout in pcb and just needed the last finish before the
board was done. Unfortunately I marked two rats nets together with
my component which I
CSB wrote:
If your design is purely combinatorial, then of course you will have
glitches, and remember that a post-fit timing simulation will show
you these glitches for the particular routing the tools just used,
which may change for each place-and-route run as you tweak the
design.
H
People,
Please ignore my last posting. It seems I had some kind of line-wrap
problem in my project file for the "gsch2pcb" command. Once I got that
corrected, the netlist appears to be correct and things look OK now.
Sorry about the confusion, and I thank you people for a very usable
product (p
Do your refdes's end in lower case letters?
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People,
Seems like I've been here before, but I can't seem to remember the
issues.
As briefly as possible, the problem is that I have a large schematic,
some 10 pages that include 8 large connectors, and 2 Xilinx, 1100 pin
fpga's. Currently, the only net that I have connected is "GND." When I
d
> If you're doing an asynchronous design, then you're on your own!
> Current CPLD and FPGA methodologies don't lend themselves well to
> async design.
> Certainly the fitted design will have glitches, as delays through
> various paths will be different. The point of synchronous design is
Stuart Brorson wrote:
My experience has been that if you are missing some system
dependencies, the first expect session will always fail, whether
running as root or not. This may be unique to the openSuSe
distributions, but I don't think so. It is more likely just an issue
exposed by the fa
My experience has been that if you are missing some system dependencies, the
first expect session will always fail, whether running as root or not. This
may be unique to the openSuSe distributions, but I don't think so. It is
more likely just an issue exposed by the fact that the openSuSe inst
Igor2 wrote:
On Sun, 18 Mar 2007, al davis wrote:
* Finally, how should PCB behave with a hierarchical
schematic?
Right click on a symbol, select "go inside", and another drawing
opens up showing what's inside. gschem also should act this
way.
I like this idea very much. I
> Couldn't resource file be used with the plugin mode of programming
> to extend function? Since it is LISP-ish it seems closest to a
> common file format language with gschem, which uses guile. Are
> there rumors of planning to stop using guile?
The resource file is purely data. Its primary
DJ Delorie wrote:
[Al Davis]>> Design the file format first,
then the data structures. The file format should be designed
as a language for expressing what you want to express.
PCB has a second format it uses called a "resource file". It's a
semi-lisp-ish format that allows for arbitrarily ne
Stuart Brorson wrote:
On Sun, 18 Mar 2007, Jason Elder wrote:
Hi, I'm having trouble with the installation, but I don't know if
this should be posted hereI just downloaded the new version
20070221 of gEDA and I was wondering how I can install it as root.
Do not install as root. If you
C P Tarun wrote:
Do not install as root. If you install as root, and you need to
install system-wide dependencies, the installer becomes confused when
it tries to fire up an expect session as root.
Now I'm confused. In all these years of working on Unix, I've always
thought packages need to
I corrected the documentation and added the TO220 pads example to
the Examples section.
Great. Thanks. :)
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Stephen Williams wrote:
I've changed your section to be one heading level down, assuming
that is your desire. Thanks for contributing.
Looks good -
Thanks
Evan
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Thank you for the post and thank you for this clarification. I do usually run
my home computer as root, but creating a user and installing this under that
user won't be a big deal. I guess I just needed the clarification for peace of
mind that I was doing the best thing for the installation.
Evan Lavelle wrote:
> Günter Dannoritzer wrote:
>> Andy Peters wrote:
>>> Does iverilog support SDF backannotation? The SDF has the delay
>>> information.
>>
>> Here are some information about that and a link to a previous discussion:
>>
>> http://iverilog.wikia.com/wiki/Graffiti#SDF_support
>
>
Evan Lavelle wrote:
> Günter Dannoritzer wrote:
[...]
>>
>> Here are some information about that and a link to a previous discussion:
>>
>> http://iverilog.wikia.com/wiki/Graffiti#SDF_support
>
> I added a section to your entry covering the reasons for doing timing
> simulations (same URL).
>
> H
On 3/19/07, C P Tarun <[EMAIL PROTECTED]> wrote:
> A script to place TO220 pads can be pretty simple (see below). The
> poorly named routine element_add_pin_oval overlays a pin, a rounded pad
> on the component side and a rounded pad on the solder side.
I have been reading your (excellently-form
Günter Dannoritzer wrote:
Andy Peters wrote:
Does iverilog support SDF backannotation? The SDF has the delay
information.
Here are some information about that and a link to a previous discussion:
http://iverilog.wikia.com/wiki/Graffiti#SDF_support
I added a section to your entry covering t
Try KJWaves (on sourceforge). The graphing routine allows you to select the
Real or Imaginary part of any signal to place on any axis of a graph. It
should do what you want. You just have to get your sim. ready to run on
ngspice.
Kurt
Wen wrote:
> Hi list,
> I am going to do Equivalent cir
On 3/19/07, C P Tarun <[EMAIL PROTECTED]> wrote:
> A script to place TO220 pads can be pretty simple (see below). The
> poorly named routine element_add_pin_oval overlays a pin, a rounded pad
> on the component side and a rounded pad on the solder side.
I have been reading your (excellently-form
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