wow i was playing with this
inkscape will use pstoedit to import ps files
this should be easier than the screen shots
On Jul 14, 2007, at 6:33 PM, Steve Meier wrote:
> Very nice!
>
> Steve Meier
>
> Ben Jackson wrote:
>> I didn't care for the PNG exporter so I laboriously made a PNG with
>> s
> Is there a way to set the line capstyle from the gschem GUI? I like
> thicker lines for non-net lines, and they look better with the
> END_ROUND capstyle.
There is a line-style rc keyword for gschem, but it appears to be
broken (does nothing that I can tell; it used to work). I have filed a
b
very pretty picture.
the better idea is to write a SVG exporter, then each layer is in
vector format, then use inkscape or any other SVG editor) to edit the
colors and stack them up.
http://en.wikipedia.org/wiki/Wikipedia:WikiProject_Electronics/
How_to_draw_SVG_circuits_using_Xcircuit
thi
Oh, very pretty picture too :-)
Possible future enhancements: Show inner layers, at least the one near
the "top". Put real FR4 color where the mask doesn't show. Use light
effects (bump map?) to get 3-D effect on copper. Use tileable brushes
to paint the copper to get real texture. Draw solde
> Any HID experts want to guess at how hard it would be to make an
> exporter that did this sort of thing automatically?
Not that hard, if you can figure out how to write a native GIMP file.
The core gives you each layer in sequence, the existing png exporter
shows you how to rasterize them. Yo
0.5mm is 20 mil pitch, there's no way you're getting two traces out
unless you've got 2/2 rules and 10 mil pads.
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Very nice!
Steve Meier
Ben Jackson wrote:
> I didn't care for the PNG exporter so I laboriously made a PNG with
> screendumps and the GIMP.
>
> http://ad7gd.net/misc/flexpretty.png
>
> Main steps:
>
> Took snapshot of only soldermask, changed color, made partially transparent.
> Used select
I didn't care for the PNG exporter so I laboriously made a PNG with
screendumps and the GIMP.
http://ad7gd.net/misc/flexpretty.png
Main steps:
Took snapshot of only soldermask, changed color, made partially transparent.
Used select by color to delete all the holes.
Took snapshot of all
If you have 25 mils of open space between pads then you can route two 5
mill width traces with 5 mills of clearence on either side and between
which meets the design requirements of my usual fab shop.
Steve M.
Steve Meier wrote:
> Harold,
>
> Can you check that again. 45 mills is 1.143 mm.
>
> Th
On Sat, Jul 14, 2007 at 04:43:38PM -0700, Andy Peters wrote:
> On Jul 14, 2007, at 11:48 AM, Steve Meier wrote:
>
> > This is an area that writting some code could be very usefull. How
> > about
> > a limited auto router that takes the bga io traces out just past the
> > nearest edge?
>
> A "fa
On Jul 14, 2007, at 11:48 AM, Steve Meier wrote:
> Hmmm,
>
> This is an area that writting some code could be very usefull. How
> about
> a limited auto router that takes the bga io traces out just past the
> nearest edge?
A "fanout" command, like what DXP and others have, is VERY useful.
-a
> How about an unstable distribution where it is guaranteed that
> nothing will work? Cool, that is my standard practice.
I've contemplated a nightly "bugs du jure" build of pcb, but never had
the time.
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Hmmm,
How about an unstable distribution where it is guaranteed that nothing
will work? Cool, that is my standard practice.
Steve M.
On Sat, 2007-07-14 at 17:52 -0400, DJ Delorie wrote:
> > Fedora is meant for cutting edge :) where bug fixes are pushed.
>
> Fedora DEVELOPMENT is for cutting ed
Harold,
Can you check that again. 45 mills is 1.143 mm.
Thanks,
Steve Meier
On Sat, 2007-07-14 at 15:43 -0500, Harold D. Skank wrote:
> Steve,
>
> You're pretty much right about every thing except the pin density.
> We're using Vertex 5, with pins spaced at 0.5 mm, pin to pin. This
> limits t
[snip]
>> And if the geda maintainers say "don't package this", then don't
>> package it. Yes, we can't stop you, but we can ask you to respect our
>> wishes and advice.
>
>
> ok !
Chitlesh and I have spoken on irc and all is well. And as I said on
irc, I'm sorry if I came across too strong and
On 7/14/07, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
> > Fedora is meant for cutting edge :) where bug fixes are pushed.
>
> Fedora DEVELOPMENT is for cutting edge. Fedora UPDATES is for stable
> stuff. Don't confuse the two, and please don't annoy our users by
> "shipping" something that's potent
> Fedora is meant for cutting edge :) where bug fixes are pushed.
Fedora DEVELOPMENT is for cutting edge. Fedora UPDATES is for stable
stuff. Don't confuse the two, and please don't annoy our users by
"shipping" something that's potentially broken, not tested, and
certainly not supported.
And
On 7/14/07, Ales Hvezda wrote:
> They are completely unstable and really only meant for people who want to see
> the
> cutting edge.
Fedora is meant for cutting edge :) where bug fixes are pushed.
Chitlesh
--
http://clunixchit.blogspot.com
___
geda-
[snip]
>Can you add up or rectify the fedora related download in the next
>release notes, please ? stating that every single development release
>of geda will be available on official fedora repositories in more or
>less 2 days time until the mirrors are synced ?
>
>One can follow when the package
On Friday 13 July 2007 14:27:37 Ales Hvezda wrote:
> Release notes:
> http://geda.seul.org/devel/v1.1/1.1.1/gaf-1.1.1-relnotes.html Download:
Can you add up or rectify the fedora related download in the next
release notes, please ? stating that every single development release
of geda will be ava
Steve,
You're pretty much right about every thing except the pin density.
We're using Vertex 5, with pins spaced at 0.5 mm, pin to pin. This
limits the routing out from each pin to essentially 1 trace between
pins.
Harold
On Sat, 2007-07-14 at 08:19 -0700, Steve Meier wrote:
> I think it is
Hmmm,
This is an area that writting some code could be very usefull. How about
a limited auto router that takes the bga io traces out just past the
nearest edge?
Steve Meier
On Sat, 2007-07-14 at 11:41 -0700, Steve Meier wrote:
> Ben,
>
> I think you have the correct idea.
>
> I would hand r
Ben,
I think you have the correct idea.
I would hand route the traces from under the fpga and perhaps around the
other major periferal chips. Then i would sort out the rats nest by
swapping io pins. After that I would let the autorouter take a shot at
the layout.
As a explination/warning about t
How about a picture from the past?
This was a 900 pin fpga where I used via in pad.
http://www.alchemyresearch.com/bga.jpg
Steve Meier
On Sat, 2007-07-14 at 10:41 -0700, Ben Jackson wrote:
> On Sat, Jul 14, 2007 at 08:19:34AM -0700, Steve Meier wrote:
> >
> > p.s. my current project uses 1020
On Sat, Jul 14, 2007 at 08:19:34AM -0700, Steve Meier wrote:
>
> p.s. my current project uses 1020 pin fpgas and was layed out on 12
> layers. One key is to be willing to swap io pins at layout time to
> minimize the need for traces to cross each other.
It would be great if someone doing advanced
I think it is the use of the autorouter then that is driving your need
for layers.
1700 pins is what an array of 42 by 42 with a 1 millimeter spacing? You
should be able to get two traces per layer in between each pair of balls.
How many IO lines are you using? xilinx vertext 3 with 1760 pads ha
Mr. Jackson,
I VERY MUCH appreciate your response and comments. In answer to your
question, "yes, I will use a 24-layer PCB if it's fully necessary."
This issue arises because the principal chip in the circuit has
something like 1700 pins and uses 3 to 4 different voltages on something
like a 45
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