I'm hacking on PCB to make the ratsnest smarter (or at least prettier)
with regard to polygons (planes).
The current code picks an arbitrary point on a rectangular polygon to
be the 'location' of that polygon. Then it participates in ratsnesting
as usual: if that one point is the closest to some
On Sun, Jul 15, 2007 at 09:50:43PM -0400, DJ Delorie wrote:
>
> > In LookupLOConnectionsToRatEnd, the r_search is just on the
> > endpoint, though.
>
> Have you tried a 3x3 box centered on the endpoint?
Now that you mention it, the find.c code actually casts a point to a
box and passes that in a
> In LookupLOConnectionsToRatEnd, the r_search is just on the
> endpoint, though.
Have you tried a 3x3 box centered on the endpoint? Anything to avoid
a linear search...
I think expanding the rtree to include the boundaries would be
acceptable for the GUI, but the autorouter uses it also, and i
On Sun, Jul 15, 2007 at 09:25:46PM -0400, DJ Delorie wrote:
>
> I wonder if giving rats a non-zero width in the rtree would help?
Rats already have a Thickness. In LookupLOConnectionsToRatEnd, the
r_search is just on the endpoint, though. And it fails the very first
test of r_search, which says
I wonder if giving rats a non-zero width in the rtree would help?
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I just filed this bug, and you can see I also found the cause and a
possible solution, but I'm surprised at how rtree works (as changed
by the patch attached to this bug).
Can someone who understands rtrees comment on the solution...
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I don't get the multiple meanings for holding down the ctrl key while
drawing a line.
It prevents the line from being drawn on the screen (why?),
it lets the last segment go off 45 degrees (hard to tell because of point
1 above), and
it lets you override the auto DRC (also hard to tell because o
Did the autoroute work? How long did it take? Are the results decent?
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Ben Jackson AD7GD
<[EMAIL PROTECTED]>
http://www.ben.com/
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On Sat, 2007-07-14 at 21:42 -0400, DJ Delorie wrote:
> > Any HID experts want to guess at how hard it would be to make an
> > exporter that did this sort of thing automatically?
>
> Not that hard, if you can figure out how to write a native GIMP file.
Gimp has a library backend, however I've nev
On Sat, 2007-07-14 at 20:34 -0700, Steven Michalske wrote:
> very pretty picture.
>
> the better idea is to write a SVG exporter, then each layer is in
> vector format, then use inkscape or any other SVG editor) to edit the
> colors and stack them up.
>
> http://en.wikipedia.org/wiki/Wikipe
On Sat, 2007-07-14 at 21:45 -0400, DJ Delorie wrote:
> Oh, very pretty picture too :-)
>
> Possible future enhancements: Show inner layers, at least the one near
> the "top". Put real FR4 color where the mask doesn't show. Use light
> effects (bump map?) to get 3-D effect on copper. Use tileab
On Jul 14, 2007, at 5:08 PM, Ben Jackson wrote:
> On Sat, Jul 14, 2007 at 04:43:38PM -0700, Andy Peters wrote:
>> On Jul 14, 2007, at 11:48 AM, Steve Meier wrote:
>>
>>> This is an area that writting some code could be very usefull. How
>>> about
>>> a limited auto router that takes the bga io tra
On Jul 15, 2007, at 9:01 AM, Stephen Williams wrote:
> DJ Delorie wrote:
>
>> In theory, via-in-pad lets you bring an extra row out on the top
>> layer. It might mean the difference between 12 and 14 layers.
>
> Also, if you avoid masking the bottom side of the via, you suddenly
> have scope acce
Looks like i need a remedial course in elementary school math.
make the pads 17 mills (.43 mm) then you have 5.2 mills between the
copper traces and the pads.
Steve M.
Steve Meier wrote:
> Harold,
>
> Try this geometry. 1 mm pitch is ~39.4 mills
>
> Make the 2 traces 4 mills make the spacing bet
DJ Delorie wrote:
> In theory, via-in-pad lets you bring an extra row out on the top
> layer. It might mean the difference between 12 and 14 layers.
Also, if you avoid masking the bottom side of the via, you suddenly
have scope access to every pad of the BGA, which I've found to be
amazingly use
> Putting a via in pad isn't necessary you can put the via between
> pads and then run your traces under the pads. The via in pad just
> gives you better usage of the surface that your device is mounted
> to.
In theory, via-in-pad lets you bring an extra row out on the top
layer. It might mean t
Putting a via in pad isn't necessary you can put the via between pads
and then run your traces under the pads. The via in pad just gives you
better usage of the surface that your device is mounted to.
Steve Meier
Harold D. Skank wrote:
> Steve,
>
> Sorry about that. I checked the Xilinx footprin
Harold,
Try this geometry. 1 mm pitch is ~39.4 mills
Make the 2 traces 4 mills make the spacing between the traces 4 mills.
make your pads 18 mills diameter.
this leaves you 5.5 mills from the edge of a trace to a pad.
Check with your fab shop I will bet they can do it using 1/2 oz copper.
5.
Steve,
Sorry about that. I checked the Xilinx footprint info and you're
correct, the spacing is 1 mm. Even so, the problem doesn't change, as
we have to use drilled pads, backfilled with epoxy. By the time you've
accounted for the sufficient pad size for chip attachment and accounted
for a 5 mi
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