Hi Andy, Steve, Dan and all,
Some time ago I gave Dan's transistor symbol generator a try and IMHO
this is the way to go.
For other parts such as opamps, triacs, diodes, caps and resistors this
will work too (the bulk of small parts up to 3 or 4 pins).
For looking up the right part I think we ne
On Dec 2, 2007, at 7:40 PM, Peter Clifton wrote:
> This is getting less "useful", but more pretty..
>
> http://www2.eng.cam.ac.uk/~pcjc2/geda/gerbv_GL.png
>
> This uses Cairo to render into a memory buffer, and then we use
> that on
> a GL context created with GtkGLExt. This allows 3D perspective
On Tue, Dec 04, 2007 at 09:21:29AM -0500, John Luciani wrote:
> Using my ancient version of PCB (2005) I created a simple PCB by placing
> my DIP-28-300 footprint on a component-side polygon. All of the pads cleared
> the polygon. When I load the file in my newer version of PCB (20070221)
> non
On Dec 4, 2007, at 8:23 PM, Steve Meier wrote:
> What is the deffinition of a heavy symbol? And secondly why put a data
> base behind one? I have been pondering this from several levels.
To me, a "heavy symbol" (or, in the parlance of other EDA packages, a
"component") is one that includes foot
What is the deffinition of a heavy symbol? And secondly why put a data
base behind one? I have been pondering this from several levels.
One level is about how heavy large components have become and the tasks
that are used in building a working programed printed circuit board.
Take a large fpga th
Steve Meier wrote:
> I am becomming more and more a proponent of heavy symbols or even a data
> base then can generate heavy symbols. One of the really nice things
> about geda is its tollerent or flexible and that heavy symbols could
> easily be implemented. So the question is... is there enough s
Randall Nortman wrote:
> I've been noticing this whole heavy vs. light debate for a while, but
> not really following it. A heavy symbol is something that is fully
> specified, including footprint, right?
Yes, with implementation details that help you check as you go towards building
it.
Stev
How?
My initial thought is something that builds a heavy library from a
light one:
Input: light/*.sym
light/*.fp
mapping table:
sym | value | device | pinmap | newsym | other-attrs
fp | value | device | pinmap | newfp | other-attrs
Output: heavy/*.sym
heavy/*.fp
We need t
On Tue, Dec 04, 2007 at 06:36:45PM -0800, Steve Meier wrote:
> I am becomming more and more a proponent of heavy symbols or even a data
> base then can generate heavy symbols. One of the really nice things
> about geda is its tollerent or flexible and that heavy symbols could
> easily be implemente
Part of the reason I ask this is that as I complete my work on a new
library, netlister et al. I am thinking that beyond having a
hierarchical schematic I would like to have symbols that can have files
such as verilog, vhdl spice etc includded and that if the netleister
could translate a schematic
I am becomming more and more a proponent of heavy symbols or even a data
base then can generate heavy symbols. One of the really nice things
about geda is its tollerent or flexible and that heavy symbols could
easily be implemented. So the question is... is there enough support in
the geda communit
On Tue, Dec 04, 2007 at 06:49:10PM -0500, Dan McMahill wrote:
> This is a known problem in the current flow. I think the right answer here
As you'll see, I don't disagree, basically, about the long-term answer.
Are there any shorter-term solutions planned, or is that the realm of a
little sed s
Martin Maney wrote:
> So I did a smallish circuit full of discrete transistors and Rs and Cs,
> and found usable footprints for all of them, but the pins from the
> transistor symbols - npn-2 and pnp-2 - didn't match the numeric pin
> names on the footprints.
Most gschem and pcb users make a libr
Martin Maney wrote:
So I've been fairly happy with these tools (currently using the
> packaged stuff from Ubuntu's Gutsy release), but there are a couple
> little things I've run into, aside from the peculiar behavior that
> arises when one tries to make an oval pin and use it in a ground
> plane.
So I've been fairly happy with these tools (currently using the
packaged stuff from Ubuntu's Gutsy release), but there are a couple
little things I've run into, aside from the peculiar behavior that
arises when one tries to make an oval pin and use it in a ground
plane...
So I did a smallish circ
David Griffith wrote:
>Does anyone have footprints for USB jacks?
>
>
>
I see that John has already chimed in, but here's another option:
Please also keep in mind the necessity for proper grounding and RFI
performance. There are app notes from Intel and Cypress which offer
some guidance. (s
I have a FCI 61729 USB-B -- not much mileage on it, though.
-dave
David Griffith wrote:
> Does anyone have footprints for USB jacks?
>
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Daniel O'Connor wrote:
> I now get..
> [inchoate 9:43] ~/work/fpga/SA >iverilog -y . -y
> $XILINX/verilog/src/unisims -y $XILINX/verilog/src/XilinxCoreLib SA_test2.v
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: syntax error
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: error: syntax error
Dan McMahill wrote:
> Stephen Williams wrote:
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA1
>>
>>
>> I've made a new release on the Icarus Verilog v0_8-branch git branch.
>> This is 0.8.6, which includes various safe fixes and updates to the
>> stable release. The source tarball and release n
I don't see anything wrong with your file. It seems that having a pad
and a pin at the same location confuses the polygon dicer. Ben?
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> Does anyone have footprints for USB jacks?
Which size? I have a mini-B...
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Kai-Martin Knaak wrote:
> On Mon, 03 Dec 2007 14:47:03 -0500, evan foss wrote:
>
>> What about brlcad? It has been in development for decades on Unix and
>> now quite a while on Linux.
>> http://my.brlcad.org/
the package's primary purpose continues to be the
> support of (1) ballistic and (2) ele
Using my ancient version of PCB (2005) I created a simple PCB by placing
my DIP-28-300 footprint on a component-side polygon. All of the pads cleared
the polygon. When I load the file in my newer version of PCB (20070221)
none of the pads clear the polygon. I have not changed the default config
On Dec 4, 2007 8:58 AM, David Griffith <[EMAIL PROTECTED]> wrote:
>
> Does anyone have footprints for USB jacks?
>
> --
> David Griffith
> [EMAIL PROTECTED]
At http://www.luciani.org/geda/pcb/pcb-footprint-list.html I have ---
CON_USB_MINI_B__Molex_67503-1020
CON_USB_TYPEB__Keystone_924
Does anyone have footprints for USB jacks?
--
David Griffith
[EMAIL PROTECTED]
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