gEDA-user: more insanity and documentation

2008-01-20 Thread DJ Delorie
I've started the second "first" board in the Getting Started manual. So far, it only goes through creating the schematic and symbols (no details on those), a footprint, and the hooks you need to tie them all together. No board work yet. This board will cover the gschem integration, custom footpr

Re: gEDA-user: Spice netlister

2008-01-20 Thread a r
On Jan 20, 2008 6:17 PM, Stuart Brorson <[EMAIL PROTECTED]> wrote: > > I have just tried the spice netlister with a trivial hierarchical > > design (a circuit that contains subcircuit that contains a MOS > > transistor). This was just before Stuart sent his mail. > > I'd be curious to see what happ

Re: gEDA-user: Spice netlister

2008-01-20 Thread Paul Tan
Hi All, On Sun, 20 Jan 2008 10:19 am, John Doty wrote: >It would be nice to be able to suppress the automatic netlist >flattening that gnetlist does, giving the back end the option of >creating a hierarchical netlist in the source= case. There is an option in system-gnetlistrc to disable flat hi

Re: gEDA-user: Spice netlister

2008-01-20 Thread a r
On Jan 20, 2008 6:19 PM, John Doty <[EMAIL PROTECTED]> wrote: > > On Jan 20, 2008, at 6:51 AM, a r wrote: > > 1. It forces me to add a simulation card to the schematic. In general > > cases that something I'd like to avoid (it is OK for testbench > > schematics, though). > > I don't see why that's

Re: gEDA-user: Spice netlister

2008-01-20 Thread John Doty
On Jan 20, 2008, at 6:51 AM, a r wrote: > I have looked closer into the sources and into the "RF_Amp" example > circuit. > > If a "spice-subcircuit-LL" component is added to the schematic the > netlister will wrap it up with a .subckt/.ends cards. That's pretty > close to the behaviour I wanted

Re: gEDA-user: Spice netlister

2008-01-20 Thread Stuart Brorson
> I have just tried the spice netlister with a trivial hierarchical > design (a circuit that contains subcircuit that contains a MOS > transistor). This was just before Stuart sent his mail. I'd be curious to see what happens if you try some of the suggestions in my e-mail. In particular, using M

Re: gEDA-user: Spice netlister

2008-01-20 Thread a r
On Jan 20, 2008 4:36 PM, al davis <[EMAIL PROTECTED]> wrote: > > > In my flow, I usually prepare a testbench file manually and > > from here I include a (clean, without simulation commands) > > netlist. However, that ".END" makes this flow awkward. Sure, > > I can do it the other way around or post

Re: gEDA-user: Spice netlister

2008-01-20 Thread al davis
On Sunday 20 January 2008, a r wrote: > Is it possible to setup gnetlist (gnetlist -g spice-sdb) so > that it won't add ".END" at the end of the spice netlist? > > In my flow, I usually prepare a testbench file manually and > from here I include a (clean, without simulation commands) > netlist. How

Re: gEDA-user: Spice netlister

2008-01-20 Thread Stuart Brorson
Hi -- > If a "spice-subcircuit-LL" component is added to the schematic the > netlister will wrap it up with a .subckt/.ends cards. That's pretty > close to the behaviour I wanted. Cool! > There are some issues, though: > 1. It forces me to add a simulation card to the schematic. In general > cas

Re: gEDA-user: Spice netlister

2008-01-20 Thread a r
On Jan 20, 2008 12:19 PM, Peter Clifton <[EMAIL PROTECTED]> wrote: > > Find this code, which is around line 1878, and comment out the line > outputting the ".end". I presume the ".ends" code is still useful.: Thanks. > ;; > ;; Now write out .END(S) of netlist, depending upon whether this schemat

Re: gEDA-user: Spice netlister

2008-01-20 Thread Peter Clifton
On Sun, 2008-01-20 at 12:12 +, a r wrote: > Hi, > > Is it possible to setup gnetlist (gnetlist -g spice-sdb) so that it > won't add ".END" at the end of the spice netlist? > > In my flow, I usually prepare a testbench file manually and from here > I include a (clean, without simulation comma

gEDA-user: Spice netlister

2008-01-20 Thread a r
Hi, Is it possible to setup gnetlist (gnetlist -g spice-sdb) so that it won't add ".END" at the end of the spice netlist? In my flow, I usually prepare a testbench file manually and from here I include a (clean, without simulation commands) netlist. However, that ".END" makes this flow awkward. S

Re: gEDA-user: Multiple user libraries, parametrized components

2008-01-20 Thread a r
On Jan 20, 2008 12:16 AM, Kai-Martin Knaak <[EMAIL PROTECTED]> wrote: > On Sat, 19 Jan 2008 20:24:42 +, a r wrote: > > First of all: What do you refer to by "cell"? A schematic symbol, or a > pcb footprint? As John said, I referred to any kind of data that belongs to a particular "block" or "c

Re: gEDA-user: string operation on path variable in gafrc

2008-01-20 Thread Kai-Martin Knaak
On Sun, 20 Jan 2008 07:11:17 +, Peter TB Brett wrote: > (define gedasymbols "/home/kmk/lilalaser/geda") (component-library > (build-path gedasymbols "analog")) Works like a charm. Thanks. I'll append this tip to the wiki. ---<(kaimartin)>--- -- Kai-Martin Knaak http://lilalaser.de/blog