> Is there a way to update the footprint in pcb like you can a
> symbol in gschem without removing the old footprint and manually
> replacing it?
Load the footprint using the library in PCB.
Rotate the footprint to match the existing one.
Position the new footprint over the old one and sh
Guys,
I have a board in layout in pcb. I've updated a footprint
external to pcb with vi.
Is there a way to update the footprint in pcb like you
can a symbol in gschem without removing the old footprint
and manually replacing it?
I'm still working on my first board in geda. Thank
Make up the pads for your pattern, add the pins add a pad with a zero
shadow mask clearence from the first pad to the pin. Give the two pads
and the pin the same pin number.
Steve Meier
Harold D. Skank wrote:
>
>
On Jan 28, 2008 9:21 PM, DJ Delorie <[EMAIL PROTECTED]> wrote:
> > Specifically we desire to have the matrix of pins offset diagonally
> > from the matrix of the pads. The pins need to be located
> > diagonally between the pad matrix and the question occurs just how
> > to interconnect the tw
> We are trying to work out details associated with separated pins
> and pads on a BGA footprint.
Pins? Or vias? Or pins in the element, used as vias?
> Specifically we desire to have the matrix of pins offset diagonally
> from the matrix of the pads. The pins need to be located
> diagon
DJ (or whomsoever),
On Jan 28, 2008 10:49 PM, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
> > Borrowing from ASIC flow: width/length, number of pins.
>
> Hmmm... elements should already know this; they have a bounding box
> and they can just count their pins.
They don't need to know it in a general case. This is called a
> Is there anything in the GUI to take advantage of this bright new
> feature? Or is it a pure ascii-edit thingy right now?
There is nothing in PCB that does *anything* with attributes, other
than to preserve them. Attributes are not for pcb itself, they are
for (as I explained) third party mod
On 01/28/2008 11:49:58 PM, DJ Delorie wrote:
> But in general, "put whatever you want in there".
Ok.
Is there anything in the GUI to take advantage of this bright new
feature? Or is it a pure ascii-edit thingy right now?
---<(kaimartin)>---
___
> Borrowing from ASIC flow: width/length, number of pins.
Hmmm... elements should already know this; they have a bounding box
and they can just count their pins.
But in general, "put whatever you want in there". It's for expansion,
third party scripts, etc.
We did suggest, when we were talking
On Jan 28, 2008 6:07 PM, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
> > What can these attributes be used for?
>
> Board level:
>
> * copyright and authorship notices
> * global state for plug-ins
> * DRC rules, post-processing settings, etc.
> * historical or tracking info (rcs tags?)
>
> Element lev
Dan McMahill wrote:
> DJ Delorie wrote:
>>> Now, what was CheckWhen intended to do and where should it go?
>> Probably should be replaced with the active= stuff. See how the grid
>> menus work.
>
> fixed.
Thanks y'all. Seems like the pcb-menu.res file was a super SW architecture
choice.
John G
DJ Delorie wrote:
>> Now, what was CheckWhen intended to do and where should it go?
>
> Probably should be replaced with the active= stuff. See how the grid
> menus work.
fixed.
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http://www.seul.org
> Now, what was CheckWhen intended to do and where should it go?
Probably should be replaced with the active= stuff. See how the grid
menus work.
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I am making some carbon ink overprinted traces with pcb, so I wanted to use
several buffers
of via and trace combinations that don't quite deserve to be footprints. I
couldn't get more
than one buffer to be saved. An error message was: no action
CheckWhen(buffer, 1)
or
no action CheckWhen(bu
> What can these attributes be used for?
Board level:
* copyright and authorship notices
* global state for plug-ins
* DRC rules, post-processing settings, etc.
* historical or tracking info (rcs tags?)
Element level:
All that plus...
* origin
* rotation
* location of documentation
Etc.
I.e.
> Is there a way to configure, what layers are actually printed during export?
It should only print layers with stuff on them (although both outside
layers are always drawn). Otherwise, just delete layers you aren't
using.
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On large devices I typically expose one pin for each required voltage
and then have a net=Vcci:G34, D27, D28 ... etc
This way the schematic shows where the device is getting each voltage
supply from without having to show large numbers of pins.
DJ proposed some time back allowing pins to have mul
On Jan 28, 2008, at 7:27 AM, Ian Chapman wrote:
> I do use the net attribute with
> off-page-connections that is with the IO out/in symbol I set net to
> sig-name:1 (invisible) and value to sig-name (visable). I wonder
> what the
> significance is of the ":1" tagged onto the end of the net val
Hi,
I never set net and netname to any value, I just leave them the way
they are in the symbol. I do use the net attribute with
off-page-connections that is with the IO out/in symbol I set net to
sig-name:1 (invisible) and value to sig-name (visable). I wonder what the
significance is of t
On Jan 28, 2008 7:23 AM, Kai-Martin Knaak <[EMAIL PROTECTED]> wrote:
> On Sat, 26 Jan 2008 13:37:44 -0500, DJ Delorie wrote:
>
> >> "for newer pcbs, a board-global Attribute() entry"
>
> What can these attributes be used for?
> A copyright notice springs to mind. What else?
keepout areas (includin
On Sat, 26 Jan 2008 13:37:44 -0500, DJ Delorie wrote:
>> "for newer pcbs, a board-global Attribute() entry"
What can these attributes be used for?
A copyright notice springs to mind. What else?
---<(kaimartin)>---
--
Kai-Martin Knaak tel: +49-511-762-2895
Univer
On Sat, 26 Jan 2008 20:09:59 -0500, DJ Delorie wrote:
> Export instead of print. Choose the postscript (ps) option. You can
> convert that to PDF.
Is there a way to configure, what layers are actually printed during
export?
---<(kaimartin)>---
--
Kai-Martin Knaak
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