On Thu, Mar 27, 2008 at 10:29:02PM -0700, Larry Doolittle wrote:
> This question has a long history. Perhaps the most notable
> discussion is the 173-long thread titled "FPGA openness" in
> 2000 in comp.arch.fpga.
BTW, I'm particulary pleased with Rickman's post
http://groups.google.com/group/
Jesse -
On Thu, Mar 27, 2008 at 08:28:29PM -0700, Jesse Gordon wrote:
> Igor2 wrote:
> > If we are at tools, I wonder... Is there an FPGA family that I could use
> > without using non-free software at all?
> >
> I was going to ask that very question. The closest I've come to "free"
> was xilin
Igor2 wrote:
>
> If we are at tools, I wonder... Is there an FPGA family that I could use
> without using non-free software at all?
>
>
I was going to ask that very question. The closest I've come to "free"
was xilinx's ISE Impact webpack which of course is only free to use and
only free for
On Thu, 27 Mar 2008, Larry Doolittle wrote:
>On Thu, Mar 27, 2008 at 09:28:23PM -0500, John Griessen wrote:
>> Larry Doolittle wrote:
>> > Self-reconfigurable FPGAs have been promised for years, but aren't
>> > ready, and probably never will be.
>> I guess that's because the fpga makers seem to
On Thu, Mar 27, 2008 at 09:28:23PM -0500, John Griessen wrote:
> Larry Doolittle wrote:
> > Self-reconfigurable FPGAs have been promised for years, but aren't
> > ready, and probably never will be.
> I guess that's because the fpga makers seem to not want to let out their
> programming details --
Larry Doolittle <[EMAIL PROTECTED]> writes:
> Assume 1mm pitch and 5/5 space/trace.
Turns out Sierra can do this, for a fee. A 7"x7" 4-layer board, with
5/5 rules and 12 mil holes, costs about $130ea qty5 if you don't mind
waiting for it. Of course, that's a $650 investment, and you still
have
Ian Chapman wrote:
> I think there is a need or it would be handy to have all versions in
> one boxsym and a few flags for low, medium, high and ridiculous pin
> counts. By ridiculous I mean you need a magnifying glass to read the
> final schematic on letter size (8.5 x 11) and I'm doing th
I think his point was - if you don't submit a proposal to Google by
Monday, you're out of the program. Working with us here on this list
(and geda-dev) will help us get to know you, and help you choose a
suitable project, but you MUST get those project proposals TO GOOGLE
by MONDAY.
___
Randall Nortman wrote:
I thought it was
> basically impossible to get it right without assistance from the CAD
> tool.
PCIe keeps the signal lines differential and regular, so you have a chance.
The open graphics project is slowly moving along -- they are motivated by
several partners
that h
Hi Peter,
I am not to sure if your are asking for projects for students to
undertake or recruiting students to undertake projects? I guess I
should look up this google summer code program and find out.
If it is the former, one thing I've been thinking about starting but
not being
Footprints
* Added footprint for API Delevan 1025 Molded Unshielded RF Coils
IND-1016P-635L-241D__API-Delevan_1025.fp
* Added footprint for the MaxStream XBee module
MOD__MaxStream_XBee.fp
* Added footprints for 3mm, 4mm, and 5mm LEDs using the Kingbright
specifications. LED_
> 1. Self-reconfigurable FPGAs have been promised for years, but aren't
> ready, and probably never will be. Think carefully about the boot
> sequence, and how one FPGA can boot the next. Having more than one
> FPGA is probably a good thing.
What about the new flash-based FPGAs? Maybe not as b
Guys -
On Thu, Mar 27, 2008 at 04:22:34PM -0700, Jesse Gordon wrote:
> DJ Delorie wrote:
>>> http://www.xilinx.com/products/boards/ml410/index.html
>> They have a lot of support chips on that board, though. Like the
>> south bridge, CF controller, PCI bridge, etc. I was thinking more
>> like "
DJ Delorie wrote:
http://www.xilinx.com/products/boards/ml410/index.html
They have a lot of support chips on that board, though. Like the
south bridge, CF controller, PCI bridge, etc. I was thinking more
like "every connector goes directly to an FPGA pin". Maybe one fpga
for the cpu
> http://geekz.co.uk/lovesraymond/archive/taking-freedom-further
Yeah, that fits.
___
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geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
> My understanding is that with the GHz busses on modern mobos you need
With a soft CPU, the busses can go slower. I wouldn't expect such a
project to compete with PCs.
> I thought it was basically impossible to get it right without
> assistance from the CAD tool.
Well, we can change the CAD t
On Thu, Mar 27, 2008 at 5:36 PM, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
> ATX motherboard (or any pc motherboard shape, really, like micro-atx
> or some laptop). PCI/PCIe slots, ISA slots, standard connectors,
> SDRAM - whatever.
>
> A huge FPGA in the middle.
>
> Or two or three big QFP one
> http://www.xilinx.com/products/boards/ml410/index.html
They have a lot of support chips on that board, though. Like the
south bridge, CF controller, PCI bridge, etc. I was thinking more
like "every connector goes directly to an FPGA pin". Maybe one fpga
for the cpu core and one for the per
On Thu, Mar 27, 2008 at 06:36:38PM -0400, DJ Delorie wrote:
>
> ATX motherboard (or any pc motherboard shape, really, like micro-atx
> or some laptop). PCI/PCIe slots, ISA slots, standard connectors,
> SDRAM - whatever.
>
> A huge FPGA in the middle.
[...]
My understanding is that with the GHz
DJ Delorie <[EMAIL PROTECTED]> wrote:
>
> ATX motherboard (or any pc motherboard shape, really, like micro-atx
> or some laptop). PCI/PCIe slots, ISA slots, standard connectors,
> SDRAM - whatever.
>
> A huge FPGA in the middle.
>
> Or two or three big QFP ones.
>
> 100% synthetic circuitry, incl
ATX motherboard (or any pc motherboard shape, really, like micro-atx
or some laptop). PCI/PCIe slots, ISA slots, standard connectors,
SDRAM - whatever.
A huge FPGA in the middle.
Or two or three big QFP ones.
100% synthetic circuitry, including a soft CPU, in a PC case.
If it's "designed for
Just a quick reminder, for those considering submitting applications to
the Google Summer of Code program, that the deadline for submissions is
Monday March 31st.
According to the timetable:
March 31: 5:00 PM PDT / 00:00 UTC April 1, 2008
Good luck everybody.
Best wishes,
--
Peter Clifton
Ele
DJ Delorie wrote:
>> "Error, too many apertures needed for Gerber file."
>
> We added a global aperture cache to work around some problems with
> certain fabs. The table has 256 entries. Your board has 315 unique
> apertures (that means, 315 total of line widths, pad widths, pin
> diameters, etc
>> "Error, too many apertures needed for Gerber file."
>
> We added a global aperture cache to work around some problems with
> certain fabs. The table has 256 entries. Your board has 315 unique
> apertures (that means, 315 total of line widths, pad widths, pin
> diameters, etc).
>
> If you want
Hi all,
I'd like to announce the science repository at the openSUSE
buildservice.
You can find some installation instructions in the wiki:
http://geda.seul.org/wiki/geda:suse_rpm_installation
The science repo contains about 55 packages related to math, electronics
and science:
* gaf packages:
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