Three thoughts.
1) Noise on power planes that isn't filtered from circuits that have
large gain in order to make very small signals big. Common types of
noise include digital clocks and switching power supplies. Noise on a
power plane gets added to the small signal and the circuits output is
somet
At 04:33 PM 4/29/2008, you wrote:
>Dan McMahill wrote:
> > If my traces were carrying ground referenced analog signals I wouldn't
> > want the power plane being my "ground" plane.
> >
> > And yes, I've seen a real life case with some rather frustrating
> > behavior that the correct stackup totally
Dan McMahill wrote:
> If my traces were carrying ground referenced analog signals I wouldn't
> want the power plane being my "ground" plane.
>
> And yes, I've seen a real life case with some rather frustrating
> behavior that the correct stackup totally fixed. There was a moment of
> clarity wh
Rick Collins wrote:
>> Question 2: In this a reasonable assignment, or am I missing something?
>> That's the stackup I use. In general, you want the ground plan near
>> the signal plane with the most signals. For surface mount, that's the
>> top. For through-hole it might be the bottom.
>
> I
Attila Kinali wrote:
> On Fri, 25 Apr 2008 14:04:38 -0700
> Stephen Williams <[EMAIL PROTECTED]> wrote:
>
>> As you know, this year's Icarus Verilog GSoC candidate is working
>> on a VHDL code generator back-end for Icarus Verilog. Hooray!
>> But suddenly the obvious question comes up, "How are we
On Tue, Apr 29, 2008 at 02:15:43PM -0400, Stuart Brorson wrote:
>
> How easy is it to fix in gsch2pcb? I haven't looked.
Don't forget that you'll want a very recent PCB if you make the most
commonly loaded PCB stackup much different from the PCB default. Without
my recent bugfix, loaded boa
On Tue, 2008-04-29 at 14:15 -0400, Stuart Brorson wrote:
> > On Tue, 2008-04-29 at 16:16 +0100, Dylan Smith wrote:
> >> On Tue, 29 Apr 2008, DJ Delorie wrote:
> >>
> >>> The problem is that gsch2pcb is using an ancient layer stack which
> >>> needs to be taken out back and shot.
> >>
> >> I'm glad
gnet-gsch2pcb.scm.in has this:
(define gsch2pcb:write-top-header
(lambda (port)
(display "# release: pcb 1.6.3\n" port)
(display "PCB(\"\" 6000 5000)\n" port)
(display "Grid(10 0 0)\n" port)
(display "Cursor(0 0 3)\n" port)
(display "Flags(0x00d0)\n" port)
(display "
> On Tue, 2008-04-29 at 16:16 +0100, Dylan Smith wrote:
>> On Tue, 29 Apr 2008, DJ Delorie wrote:
>>
>>> The problem is that gsch2pcb is using an ancient layer stack which
>>> needs to be taken out back and shot.
>>
>> I'm glad I'm not the only one who thought that, and did as you suggest
>> (paste
On Tue, 2008-04-29 at 16:16 +0100, Dylan Smith wrote:
> On Tue, 29 Apr 2008, DJ Delorie wrote:
>
> > The problem is that gsch2pcb is using an ancient layer stack which
> > needs to be taken out back and shot.
>
> I'm glad I'm not the only one who thought that, and did as you suggest
> (paste in t
At 11:57 AM 4/29/2008, you wrote:
> > Turns out that for the purpose of impedance a power plane is exactly
> > the same as a ground plane.
>
>That's true unless you have a split power plane.
Only if the split power planes are nowhere near the ground plane. If
there is significant overlap and th
> Turns out that for the purpose of impedance (which is why you want
> your traces close to the plane) a power plane is exactly the same as
> a ground plane.
..or, at least, if it's not, you need better power bypassing. :)
/~\ The ASCII der Mouse
\ / Ribbon Campaign
X
> Turns out that for the purpose of impedance a power plane is exactly
> the same as a ground plane.
That's true unless you have a split power plane.
The whole field of high speed PCB layout is much more complex than is
warranted on this list, which is why I made a sweeping generalization.
I thi
At 10:53 AM 4/29/2008, you wrote:
> > Question 1: Each "Group" will be a physical layer of copper, correct?
>
>Yes.
>
> > Question 2: In this a reasonable assignment, or am I missing something?
>
>That's the stackup I use. In general, you want the ground plan near
>the signal plane with the most
On Tue, 29 Apr 2008, DJ Delorie wrote:
> The problem is that gsch2pcb is using an ancient layer stack which
> needs to be taken out back and shot.
I'm glad I'm not the only one who thought that, and did as you suggest
(paste in the output).
___
geda-u
> Umm, DJ, since you use this stackup, and it is the logical one, is
> there any reason why this is not the default presented to the user
> when PCB starts from scratch?
The default layer grouping is:
component
solder
gnd
power
signal1
signal2
signal3
signal4
This makes sense for the most c
> I want to make a 4-layer board with the middle two layers being ground
> and power, so to my way of thinking the following is a reasonable layer
> and group assignment (I'm not using any surface mount devices on this
> particular board):
>
> Group 1: component, component side
> Group 2: GND
>
Ben Jackson wrote:
> On Tue, Apr 29, 2008 at 12:19:55AM -0400, DJ Delorie wrote:
>> io.pcb
>> 3594,2241
>> component side
>
> Ok, I see it now. There's a 45 degree line segment near 'U303' (the text)
> which is two segments. The polygon code is not happy about that. If you
> make it one continu
> In PCB, looking under File->Preferences, then Layers, Groups shows four
> default groups.
>
> Group 1 is solder, Vcc-solder, GND-solder
> Group 2 is component, Vcc-comp, GND-comp
> Group 3 is "solder side"
> Group 4 is "component side"
Actually, PCB's grouping concept is kind of confusing, I
On Mon, 28 Apr 2008 14:09:25 -0700, Greg Bengeult wrote:
> Is there any good way to put silkscreen text on the back (solder) side
> of a board? I have a very dense PCB with no room left for the model
> number, serial number, copyright text, etc. on the front.
This is covered in the wiki:
http://
> Question 1: Each "Group" will be a physical layer of copper, correct?
Yes.
> Question 2: In this a reasonable assignment, or am I missing something?
That's the stackup I use. In general, you want the ground plan near
the signal plane with the most signals. For surface mount, that's the
top.
Hi,
In PCB, looking under File->Preferences, then Layers, Groups shows four
default groups.
Group 1 is solder, Vcc-solder, GND-solder
Group 2 is component, Vcc-comp, GND-comp
Group 3 is "solder side"
Group 4 is "component side"
Question 1: Each "Group" will be a physical layer of copper
Attila Kinali wrote:
> On Fri, 25 Apr 2008 14:04:38 -0700
> Stephen Williams <[EMAIL PROTECTED]> wrote:
>
>> As you know, this year's Icarus Verilog GSoC candidate is working
>> on a VHDL code generator back-end for Icarus Verilog. Hooray!
>> But suddenly the obvious question comes up, "How are we
On Fri, 25 Apr 2008 14:04:38 -0700
Stephen Williams <[EMAIL PROTECTED]> wrote:
> As you know, this year's Icarus Verilog GSoC candidate is working
> on a VHDL code generator back-end for Icarus Verilog. Hooray!
> But suddenly the obvious question comes up, "How are we going to
> run these generate
Hello.
Am 29.04.2008 um 01:23 schrieb Stephen Williams:
> Attila Kinali wrote:
>> On Sat, 26 Apr 2008 09:22:17 +0200
>> Hagen SANKOWSKI <[EMAIL PROTECTED]
>> > wrote:
>
>>> Mostly bad VHDL design goes to FPGA, good Verilog design goes to
>>> ASICs.
>>
>> Uhm... I don't think i have to comment
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