ok,
So if I have correctly understood, the symbol provided with gEDA are
designed to do PCB, not simulation.
In case of simulation, it's simpler to have symbol with all pins (power
included), in to order to netlist correctly.
I will check with a custom symbol with power pin and I reply to you ab
Tried to send this to DJ directly, but that's not going to work...
On Sat, Aug 16, 2008 at 06:26:16PM -0400, DJ Delorie wrote:
>
>
> I
On Sat, 2008-08-16 at 15:59 -0400, John Doty wrote:
> On Aug 16, 2008, at 3:32 PM, John Doty wrote:
>
> > Hmm, I wonder if the problem is the hidden power pins,
>
> I note that it there is no mechanism to tell gnetlist what subcircuit
> pin a hidden net should attach to.
You are correct. Remov
On Sat, 2008-08-16 at 16:29 -0400, John Doty wrote:
> On Aug 16, 2008, at 4:21 PM, Peter Clifton wrote:
>
> > Please could you post the full console output of the gnetlist run.
>
> He did, at the start of this thread 2.5 days ago. Also the schematic.
So he did.. I came in at the end there.
_
Jared Casper wrote:
> On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer <[EMAIL PROTECTED]>
> wrote:
>> So with the latest development snapshot it gave me an assertion, but
>> with the git version a segmentation fault.
>>
>
> I saw this behavior as well, so I don't think it is your setup. Som
On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer <[EMAIL PROTECTED]> wrote:
> So with the latest development snapshot it gave me an assertion, but
> with the git version a segmentation fault.
>
I saw this behavior as well, so I don't think it is your setup. Something must
have changed in git
On Aug 16, 2008, at 4:21 PM, Peter Clifton wrote:
> Please could you post the full console output of the gnetlist run.
He did, at the start of this thread 2.5 days ago. Also the schematic.
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
[EMAIL PROTECTED]
_
On Sat, 2008-08-16 at 20:53 +0200, Ludovic SMADJA wrote:
> About the unused slots, it doesn't seems to be the problem.
>
> When I add the 2 unused slots to my schematics and link theirs input
> pins to ground and output pin to NC symbol, drc2 removes the warning
> but the spice-sdb give me more "
On Aug 16, 2008, at 3:32 PM, John Doty wrote:
> Hmm, I wonder if the problem is the hidden power pins,
I note that it there is no mechanism to tell gnetlist what subcircuit
pin a hidden net should attach to.
Again, it is strange to use a symbol designed for slotted printed
circuit layout in
Stephen Williams wrote:
> Günter Dannoritzer wrote:
...
>>
>> How can I check that it works correct?
>
> It is just as likely that you found a bug that is segfaulting instead
> of tripping an assert. That is rare in Icarus Verilog because we're
> so liberal with assertions, but it does happen from
Hmm, I wonder if the problem is the hidden power pins, combined with
slotting. Oh, Stuart...
On Aug 16, 2008, at 2:53 PM, Ludovic SMADJA wrote:
> About the unused slots, it doesn't seems to be the problem.
>
> When I add the 2 unused slots to my schematics and link theirs
> input pins to grou
Stephen Williams wrote:
> I think there is a bug report related to this in the icarus verilog
> bugs tracker already. "automatic" tasks are not supported yes, and
> there is a patch that I recently applied that reports this as a
> proper error.
Are there any plans to add automatic tasks or is that
About the unused slots, it doesn't seems to be the problem.
When I add the 2 unused slots to my schematics and link theirs input pins to
ground and output pin to NC symbol, drc2 removes the warning but the
spice-sdb give me more "Invalid wanted_pin passed to get-nets [unknown]"
I've already use s
On Sat, 2008-08-16 at 09:26 -0400, John Doty wrote:
> On Aug 16, 2008, at 2:55 AM, Ludovic SMADJA wrote:
>
> > WARNING: Unused slot 3 of uref U2
> > WARNING: Unused slot 4 of uref U2
>
> I believe that unused slots are poison to the way spice-sdb works.
> For a slotted component, it expects tha
Günter Dannoritzer wrote:
> Hi,
>
> I tried to install Icarus Verilog from git and wonder whether I did
> something wrong, as when things go wrong it crashes with a segmentation
> fault.
>
> I have to say that I have the latest development snapshot installed in
> parallel in the standard path.
I think there is a bug report related to this in the icarus verilog
bugs tracker already. "automatic" tasks are not supported yes, and
there is a patch that I recently applied that reports this as a
proper error.
Günter Dannoritzer wrote:
> Hi,
>
> I tried compiling some Verilog code with a 'tas
On Aug 16, 2008, at 2:55 AM, Ludovic SMADJA wrote:
> WARNING: Unused slot 3 of uref U2
> WARNING: Unused slot 4 of uref U2
I believe that unused slots are poison to the way spice-sdb works.
For a slotted component, it expects that the model will implement all
slots. Since pins are positional
On Sat, 2008-08-16 at 08:56 +0200, Ludovic SMADJA wrote:
> Note I've not precised in my precedent post, I use generic schematic
> with slot (without slot, it's working well, and custom symbol with
> slot is working well).
>
> Ludovic
>
> On Sat, Aug 16, 2008 at 8:55 AM, Ludovic SMADJA
> <[EMAIL P
Note I've not precised in my precedent post, I use generic schematic with
slot (without slot, it's working well, and custom symbol with slot is
working well).
Ludovic
On Sat, Aug 16, 2008 at 8:55 AM, Ludovic SMADJA <[EMAIL PROTECTED]>wrote:
> Yes I've followed the tutorial you linked,
>
> gsymch
Yes I've followed the tutorial you linked,
gsymcheck give no errors for the sym I use (generic 7408 sym provided with
geda)
for drc2 check, I've already done it and the result is some warning :
WARNING: Pin(s) with pintype 'output': U2:6
are connected by net 'unnamed_net11'
to pin
20 matches
Mail list logo
