Dan -
On Tue, Feb 17, 2009 at 10:01:57PM -0500, Dan McMahill wrote:
> The tool worked and really my primary complaint was that you quickly
> ended up with an expression that
> a) was not at all a low entropy expression (see various papers by
> Middlebrook or the textbook by Vorperian)
Hey! I s
> If anyone would have a clue on how to contact Henry Yiu it might be
> interesting to see if he would provide a license that allows for
> redistribution.
Did you try the addr on this web page?
http://www.geocities.com/hyiu00/
Stuart
___
geda-user ma
al davis wrote:
> Another interesting type of analysis that Spice doesn't have is
> a semi-symbolic analysis, where the result is a transfer
> function, in S, that has some values carried through as
> symbols. I would have to help you a lot, but it would be a
> real accomplishment, and I think
[snip]
>I'll try the 2nd in the immediate term, but it makes me nervous to use
>a netlister with a known bug.
I have filed a bug ("artifact" as the new sf tracker likes to
call them) on this issue (#2611098).
-Ales
__
Got it to build and work.
Sorry about that.
Pete
On Feb 17, 2009, at 8:37 PM, DJ Delorie wrote:
>
> Pleas read README.cvs
>
>
> ___
> geda-user mailing list
> geda-user@moria.seul.org
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Peter Wil
Pleas read README.cvs
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I grabbed the had branch from the git repository, got configure to run
and when I run make I get the following error (see below). I think
some images are missing when it runs the make file in the doc sub
directory?
Pete
Making all in doc
make all-am
rm -rf pcb.htp
if /bin/sh /Users/Pete/s
On Tue, 2009-02-17 at 11:29 +0100, Denis Grelich wrote:
> On Mon, 16 Feb 2009 12:34:15 -0800
> Ben Jackson wrote:
> > On Mon, Feb 16, 2009 at 02:56:44PM +0100, Denis
> Grelich wrote:
> > >
> > > First there's a problem with polygon clearance.
> >
> > I think that might be a GL display bug. Ther
> Yes, that will work. What script language are you going to use?
> Please tell us what happens.
>
> John Griessen
Hi John,
Well, I'm fairly proficient at java so that's how I'm doing it. It
should take me very long to put it together.
gene
___
On Tue, Feb 10, 2009 at 4:23 PM, Stephen Williams wrote:
> Matt Ettus wrote:
>> In some Xilinx models, they make instantiations like this:
>>
>> block instance(ports);
>> defparam instance.param=VALUE
>>
>>
>> This normally works ok. The problem is that inside the block,
>> generate statements ar
On Tue, 2009-02-17 at 13:29 -0800, Ben Jackson wrote:
> On Tue, Feb 17, 2009 at 09:08:33PM +, Peter Clifton wrote:
> > >
> > > I think the only straightforward way to fix the self-intersecting arc is
> > > to build it internally from two parts and union them. Might be slow on
> > > teardrop'd
On Tue, 2009-02-17 at 13:29 -0800, Ben Jackson wrote:
> On Tue, Feb 17, 2009 at 09:08:33PM +, Peter Clifton wrote:
> It usually boils down to numerical instability in the polygon code.
> I may have an example. I save all the strange boards people send in with
> bug reports to use as regressio
On Tue, Feb 17, 2009 at 09:08:33PM +, Peter Clifton wrote:
> >
> > I think the only straightforward way to fix the self-intersecting arc is
> > to build it internally from two parts and union them. Might be slow on
> > teardrop'd boards.
>
> Probably just need some simple geometry to work ou
On Tue, 2009-02-17 at 12:58 -0800, Ben Jackson wrote:
> On Tue, Feb 17, 2009 at 08:02:42PM +, Peter Clifton wrote:
> >
> > I think the first hint of trouble is exemplified by PCB's failure to
> > clear this the 360 degree arc from the polygon. I've distilled a
> > test-case from your example (
Did you check the wiki? Although the pcb section is called "tips" it
is more like FAQ. For your particular question:
[1]http://geda.seul.org/wiki/geda:pcb_tips#why_is_it_possible_to_make_
a_thermal_for_pin_but_not_for_a_pad
using the ground plane as the GND netlist?
[2]http:
On Tue, Feb 17, 2009 at 08:02:42PM +, Peter Clifton wrote:
>
> I think the first hint of trouble is exemplified by PCB's failure to
> clear this the 360 degree arc from the polygon. I've distilled a
> test-case from your example (attached).
Yes, as soon as he said it I figured that the self-i
On Tue, 17 Feb 2009 17:11:53 +0100, Stefan Salewski wrote:
> this is 3.2*2.6*123 = 1023.36 Euro for one board.
Look for the "Sparklasse". This assumes a per panel pricing. You get what
ever number of identical PCBs fit onto on a panel for more or less fixed
price. They keep your data. So the se
On Tue, 17 Feb 2009 16:42:12 +, carzrgr8-p32f3XyCuykqcZcGjlUOXw wrote:
> I'm pretty sure this idea is going to work. My design, although large
> in component count, is really just a bunch of identical blocks repeated
> many times.
http://geda.seul.org/wiki/geda:pcb_tips#is_there_a_way_to_do_
On Tue, 17 Feb 2009 19:33:35 +, Peter Clifton wrote:
> By the way: How can I set similar names that deviate from the
>> path for my local libs?
>
> An optional final argument on the command which instantiates the library
Thanks.
---<(kaimartin)>---
__
carzr...@optonline.net wrote:
> 6. Filter the file, renaming all the 'selected' parts that match 'S1/S101'
> with 'S2/S101'.
>
> Assuming it works, I want to say that PCB file format makes stuff like this
> pretty easy!
>
> gene
Yes, that will work. What script language are you going to u
On Mon, 2009-02-16 at 14:58 +0100, Denis Grelich wrote:
> Sorry, forgot to actually attach the screenshot and the example ;)
That's pretty broken looking..
I think the first hint of trouble is exemplified by PCB's failure to
clear this the 360 degree arc from the polygon. I've distilled a
test-ca
Hi all,
On Mon, 2009-02-16 at 20:23 -0500, DJ Delorie wrote:
> > Maybe I'm overlooking something very obvious and better should restart
> > tomorrow morning after some coffee.
>
> Close! Elements don't always have names. You also didn't check for
> missing arguments. Try this bit of code:
>
>
On Mon, 2009-02-16 at 14:57 +, Kai-Martin Knaak wrote:
> On Sat, 24 Jan 2009 14:51:54 +0530, Shakthi Kannan wrote:
>
> > http://geda.seul.org/wiki/geda:gsch2pcb_tutorial
> >
> > * There is no "Analog" library under Components. Under "Basic" devices,
> > we have resistor-1.sym.
>
> I accommod
The mark in a paste is the origin of the cut (and thus of the paste
too), usually the crosshair position when you cut it or mark when you
save a pcb. My scripts always zero that out (Cursor[] in the *.pcb)
before pasting layouts so I get consistent results, otherwise the
pasted regions may be off
On Tue, Feb 17, 2009 at 04:42:12PM +, carzr...@optonline.net wrote:
>
> So here's the plan:
> 1. Place and route all the parts of one hierarchical block, for example
> S1/S101.
> 2. Select all the parts from S2/S101 and delete them ( I don't think there's
> a 'delete
> selected' menu, but '
> Depending on the order of the schematics on the gnetlist line, you will
> get a different net renamed (DVDD_FPGA -> Vcco2 or DVDD_FPGA -> Vcco3).
>
> This is most certainly a bug in gnetlist and probably has been there
> since the beginning of time. I am guessing it worked in the past due
> to s
I just sent out a board which I had quoted on FR4 and Rogers 4350.
The Rogers material was more expensive, but for sure not 4x more. I
won't get the boards back for a couple days yet, but I've seen other
proto's they did for us (on .031" Rogers 4350 w/ immersion silver
plating) and
I'm pretty sure this idea is going to work. My design, although large in
component count,
is really just a bunch of identical blocks repeated many times. For example,
there's an
input buffer section that's copied 8 times. Each of those buffers has a
hierarchical
reference designator, say S
Am Dienstag, den 17.02.2009, 14:41 + schrieb Kai-Martin Knaak:
> On Mon, 16 Feb 2009 21:11:30 +0100, Stefan Salewski wrote:
>
> > Yes, but total costs are still not bad. If I remember correctly: Four
> > boards, 4 layer, each 26cm * 32cm will give total something about 1000
> > Dollar.
>
> My
Gabriel -
On Tue, Feb 17, 2009 at 03:47:10PM +0100, Gabriel Paubert wrote:
> Did not nee for this, and my RF designs use Rogers' substrates which
> are much more reproducible than FR4 at frequencies above 2GHz.
I'm currently searching for a U.S. fab for prototype quantity
of Rogers' boards that d
On Mon, Feb 16, 2009 at 09:11:30PM +0100, Stefan Salewski wrote:
> Am Montag, den 16.02.2009, 18:53 + schrieb Kai-Martin Knaak:
> >
> > Some remarks:
> >
> > * 4 Layers will take 12 working days minimum, plus what ever it takes for
> > fedex to ship from china. If you don't register for "op
On Tue, 17 Feb 2009 02:12:47 -0500, al davis wrote:
> People spend lots of time trying to make a GUI, when there are problems
> underneath.
Is this true in this special case? (Doing gnucap sims with schematics
designed with gschem)
I got the impression, that all the infrastructure is there, but
On Mon, Feb 16, 2009 at 05:36:02PM +0100, Stefan Salewski wrote:
> Am Montag, den 16.02.2009, 09:50 + schrieb Dylan Smith:
> > On Sat, 14 Feb 2009, Dave N6NZ wrote:
> >
> > On Chinese fabs...
> >
> > > So... it's hard to beat BatchPCB's price for one-offs, but I've decided
> > > to dial back
On Mon, 16 Feb 2009 21:11:30 +0100, Stefan Salewski wrote:
> Yes, but total costs are still not bad. If I remember correctly: Four
> boards, 4 layer, each 26cm * 32cm will give total something about 1000
> Dollar.
My favorite Germany based fab, Basista, quotes 992.92 EUR for 5 such
boards, shipp
On Tue, 17 Feb 2009 09:18:51 +1100, Susan Mackay wrote:
> Thanks for that - Is this documented anywhere
Did you check the wiki? Although the pcb section is called "tips" it
is more like FAQ. For your particular question:
http://geda.seul.org/wiki/geda:pcb_tips#why_is_it_possible_to_make_a_ther
On Mon, 16 Feb 2009, Kai-Martin Knaak wrote:
>Just checked it.
>
>Some remarks:
>
I have actually used PCB Cart, and found them to be good value and do a
nice job - I had them make ten 4 layer 100x60mm boards with 6/6
rules. No faults (all electrically tested), arrived very well packed,
and with
[snip]
>I will try making a smaller test case again, but haven't had luck so
>far. I would feel better if I knew that you saw the problem in the
>netlist I sent.
>
Okay, I am now able to reproduce the problem with the following
attached schematics. I generally do not like to netlist sch
On Feb 17, 2009, at 2:12 AM, al davis wrote:
> Another interesting type of analysis that Spice doesn't have is
> a semi-symbolic analysis, where the result is a transfer
> function, in S, that has some values carried through as
> symbols. I would have to help you a lot, but it would be a
> real
On Mon, 16 Feb 2009 12:34:15 -0800
Ben Jackson wrote:
> On Mon, Feb 16, 2009 at 02:56:44PM +0100, Denis
Grelich wrote:
> >
> > First there's a problem with polygon clearance.
>
> I think that might be a GL display bug. There was a thread about that
> recently. Try exporting your layout to Post
I added an option to djboxsym to format labels for pins on the top and
bottom edges of the symbols vertically, rather than the default
horizontally. This seems to work better for chips with lots of
power/ground symbols, or in cases where you want a physical
representation of a QFN chip.
http://w
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