On Sat, 2009-11-14 at 18:18 -0600, John Griessen wrote:
> I'd like to know if the plugin method can create a trace segment
> that will DRC to be a connected gnetlistable trace as is. IOW is there an
> action command
> to create a line segment?
You don't need an action command to do it.. plugins
DJ Delorie wrote:
>> What if a plugin created line segments to approximate ellipses and splines?
>
> PCBs plugin structure doesn't allow for adding tools or object types,
> just actions and hids.
OK. Actions can create lines can't they? If so, maybe a plugin is a way
to get many little line seg
On Sat, Nov 14, 2009 at 6:10 PM, Bert Timmerman wrote:
> Hmm, I would not know how to update an iso image for a liveDVD with
> yum ;(
Either try to create a liveusb from the livedvd ( 2 - 4 mins work).
https://fedorahosted.org/fedora-electronic-lab/wiki/developers#CreatingaFELLiveUSB
> Does there
On Sat, 2009-11-14 at 13:09 -0800, John Eaton wrote:
> However it is in your best interest to specify exactly how you want
> them routed, and/or scored,
> by known you Contract Assemblers needs.
>
>
>Do not let your board house tel
However it is in your best interest to specify exactly how you want
them routed, and/or scored,
by known you Contract Assemblers needs.
Do not let your board house tell you that their router bit is 1/8" and
make that
you
On Sat, Nov 14, 2009 at 7:01 AM, DJ Delorie wrote:
>
> Stack issues?
>
> http://www.geda.seul.org/wiki/geda:faq-gnetlist
This has been happening for years. Why not just make the default
stack bigger and avoid the problem in the first place?
Matt
__
Hi Chitlesh,
On Sat, 2009-11-14 at 17:20 +0100, Chitlesh GOORAH wrote:
> On Thu, Nov 12, 2009 at 8:00 PM, Bert Timmerman wrote:
> > I just test drove FEL-11, and IIRC there is a 2008-ish version of pcb
> > included.
>
> Actually the latest version of pcb is among the fedora 11 and 12 updates :)
> Most FAB's I've come across would rather do the panellising themselves,
> as they will no doubt have their own process rules about spacing, adding
> routing between the boards etc.
Panellising (what is the correct spelling for that, as there doesn't
seem to be one?)
is best left done to the boar
On Thu, Nov 12, 2009 at 8:00 PM, Bert Timmerman wrote:
> I just test drove FEL-11, and IIRC there is a 2008-ish version of pcb
> included.
Actually the latest version of pcb is among the fedora 11 and 12 updates :)
for EPEL-5, the latest version is in el5-testing repo
https://admin.fedoraproject
DJ Delorie wrote:
> Stack issues?
>
> http://www.geda.seul.org/wiki/geda:faq-gnetlist
>
BINGO!
Following the instructions, I had to edit the .scm file to make it work.
thanks
gene
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Stack issues?
http://www.geda.seul.org/wiki/geda:faq-gnetlist
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Hi everyone,
Just to let you know, that Andrey Smirnov has added support for writing
config settings into your gsch2pcb project file from within xgsch2pcb.
This means you can adjust footprint search paths, M4 vs. non-M4 file
search order preferences, and many more advanced options present in the
I've tried this in both version 1.4.0 release and 1.5.2, with different
messages, but all fail. I've tried
gnetlist -g partslist
gnetlist -g partslist1
gnetlist -g partslist2
gnetlist -g partslist3
and all fail. Any help?
Here's the output from gnetlist -g partslist1 (partslist2 partslist3
sa
On Sat, 2009-11-14 at 13:59 +, Peter Clifton wrote:
> On Fri, 2009-11-13 at 23:27 -0500, Tony Radice wrote:
>
> > Issue:
>
> As Ineiev said, I think this bug has been fixed in git HEAD - if you
> wanted to try that.
>
> (And with my GL branch, the board rendering isn't so slow either!)
>
>
On Fri, 2009-11-13 at 23:27 -0500, Tony Radice wrote:
> Issue:
As Ineiev said, I think this bug has been fixed in git HEAD - if you
wanted to try that.
(And with my GL branch, the board rendering isn't so slow either!)
Also, your panel has its layer groups messed up, again - as Ineiev
pointed
Hello,
One more note about teardrops. The plugin is really nice and helpful for
home-made boards. It helps keep all the connections right and prevents lifting
up tracks when holes are drilled a bit off-center.
Best Regards,
Michael W.
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On 11/14/09, Ineiev wrote:
> (2) the bug was fixed recently, as I used a post-20091103 GIT version.
> can you check the current GIT head?
Well, this case I can check myself; and it appears that two polygons
on "solder" layer do disappear on loading the file; as I mentioned,
the bug was fixed in c
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