Done. Thank you gentlemen. I understand queries such as mine are
"clutter" in high quality list traffic, such as found here. Other such
lists have mercilessly sent me to /dev/null in the past. I appreciate
your kindness in responding.
On Wed, Jan 6, 2010 at 12:15 AM, John Griessen
On Tue, Jan 05, 2010 at 10:08:15PM -0500, Stan Katz wrote:
>
>I use gEDA for small projects. One, and two sided boards only. It's
>been fine up until now. I now have a transceiver chip with some pins,
>a number of which I need to run to pin 1 on an IDE header. No matter
>how I dra
Stan Katz wrote:
No matter
>how I draw the nets in gschem, the final rats nest runs produced in
>pcb is one trace, across all the pins on each side of the SOIC, as
>long as any of them are in the star end-run to the header pin. In
>other words, if I want to tie pins 1,3,5, of the
Rats don't short copper they travel across; they only electrically
connect their endpoints. It's up to you - the layout person - to put
copper (not rats) in the right places. PCB has some settings to help
with this, like auto-enforce DRC clearance which highlights pins in
the same net when you s
I use gEDA for small projects. One, and two sided boards only. It's
been fine up until now. I now have a transceiver chip with some pins,
a number of which I need to run to pin 1 on an IDE header. No matter
how I draw the nets in gschem, the final rats nest runs produced in
pcb is
Hi Vincent,
As DJ already mentioned, keep the source trees on a correct level.
Clues to be found at :
http://github.com/bert/pcb-plugins/commit/3ef110ba3ec428c67111f19ece4de89d51
b5f418
Kind regards,
Bert Timmerman.
-Oorspronkelijk bericht-
Van: geda-user-boun...@moria.seul.org
[mailt
On Tuesday 05 January 2010 18:31:49 DJ Delorie wrote:
> > Can't wait to have that one implemented as it's the one point i
> > tripped over with about every software i tried.
>
> Just to be clear - by writing down my ideas, I do not mean to imply
> that I (or anyone else) will actually implement th
On Jan 5, 2010, at 9:31 AM, DJ Delorie wrote:
>
>> Can't wait to have that one implemented as it's the one point i
>> tripped over with about every software i tried.
>
> Just to be clear - by writing down my ideas, I do not mean to imply
> that I (or anyone else) will actually implement them.
> Can't wait to have that one implemented as it's the one point i
> tripped over with about every software i tried.
Just to be clear - by writing down my ideas, I do not mean to imply
that I (or anyone else) will actually implement them.
___
geda-user
On Tuesday 05 January 2010 17:45:17 DJ Delorie wrote:
> > Maybe i missed it, but I haven't seen a reference to something I'd
> > call global gate swapping.
>
> Assigning gates to packages is one of the things left up to the
> netlister (choosing) and pcb (swapping) now.
>
> > So, is there a sensi
> Maybe i missed it, but I haven't seen a reference to something I'd
> call global gate swapping.
Assigning gates to packages is one of the things left up to the
netlister (choosing) and pcb (swapping) now.
> So, is there a sensible way to leave decision actual packages and
> relations between s
On Sun, 27 Dec 2009 21:46:07 -0800, Anthony Shanks wrote:
> This worked! Thanks
Did you write a bug report on this?
IMHO, this needs to be fixed. The work-flow should not break if the
project grows beyond some reasonable size.
--<(kaimartin)>---
--
Kai-Martin Knaak
I am starting a small electronics company and I need to hire a geda
expert to help make some pcb designs. I already have a few ideas
lined up and I am willing to pay well. Please email me back if anyone
is interested.
Jason from shenzhen
__
On Sunday 27 December 2009 04:11:57 DJ Delorie wrote:
> I took the time to document my ideas about heavy vs light symbols and
> the pin mapping problem:
>
> http://www.delorie.com/pcb/component-dbs.html
> http://www.delorie.com/pcb/pin-mapping.html
>
At first, let me thank DJ for writing it all d
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