Hello fellow free EDA users,
I wonder, would there happen to be anyone on this list who has a working
flash chip programmer setup and who would be willing to help out a
fellow Open Source Hardware maker, for some monetary compensation for
your time and effort?
I need to have some 29F040 type flas
Eric Brombaugh wrote:
> I ran this through Modelsim LE and got the following result:
>
> # -7.093308,7.093308,7.093308,7
>
> Running it through my copy of Icarus 0.9.2 gives the same answer you got
> above, so I'm guessing that there's something odd going on with the way
> Icarus is parsing compl
On Jul 1, 2010, at 8:41 AM, hari venkatesh wrote:
> I want to simulate a rectifier circuit in gEDA, while i am generating
> the netlist for the circuit.
> i have given the refdes as T1, during netlist generation it is giving
> error, refdes=T1 not found
> Could u please mail me the list
That comment looked like sarcasm to me.
> -Original Message-
> From: geda-user-boun...@moria.seul.org
> [mailto:geda-user-boun...@moria.seul.org] On Behalf Of DJ Delorie
> Sent: Thursday, July 01, 2010 11:37 AM
> To: gEDA user mailing list
> Subject: Re: gEDA-user: volunteers wanted in
> It is very generous of you to provide transportation and accommodations.
What made you think I was doing that?
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> What is the name of the conference?
http://www.renesasdevcon.com/
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On Thu, 1 Jul 2010 20:11:53 +0530
hari venkatesh wrote:
> I want to simulate a rectifier circuit in gEDA, while i am generating the
> netlist for the circuit.
>
> i have given the refdes as T1, during netlist generation it is giving error,
> *refdes=T1* not found
>
> Could u please mail me the
On 07/01/2010 06:10 AM, Patrick Doyle wrote:
When I run the following code in Icarus Verilog:
`define Tnom 140e-9
`define Rele 2e3
`define Cele 0.3e-6
`define Vdd1p8 1.7
`define DrvIstep 1e-6
`define ADCScale (1024/`Vdd1p8*`DrvIstep)
module check_this();
integer pulse_dur = 15;
integer delta3
I want to simulate a rectifier circuit in gEDA, while i am generating
the netlist for the circuit.
i have given the refdes as T1, during netlist generation it is giving
error, refdes=T1 not found
Could u please mail me the list attributes that should be attached for
the transforme
It is very generous of you to provide transportation and accommodations.
On 07/01/2010 01:04 AM, DJ Delorie wrote:
In October I'm going to be giving a presentation at a conference, and
I'll be talking about open source EDA. Part of the deal is I get a
booth in the trade show area. Since I have
When I run the following code in Icarus Verilog:
`define Tnom 140e-9
`define Rele 2e3
`define Cele 0.3e-6
`define Vdd1p8 1.7
`define DrvIstep 1e-6
`define ADCScale (1024/`Vdd1p8*`DrvIstep)
module check_this();
integer pulse_dur = 15;
integer delta3 = 1;
integer drvw1 = -20;
initial begin
$displ
On Thu, Jul 1, 2010 at 1:04 AM, DJ Delorie wrote:
> In October I'm going to be giving a presentation at a conference
What is the name of the conference?
(* jcl *)
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