Ringing it with copper certainly would work. PCB doesn't have a
generic "keep out" feature yet.
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Is there a way to "protect" the fiducial? For example I could attempt
to ring it with copper.
Oliver
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From: DJ Delorie
To: gEDA user mailing list
Sent: Sat, December 4, 2010 11:29:28 PM
Subject: Re: gEDA
Two notes:
1. "Clearance" is clearance in polygons, not the line/space rule.
2. Add the "nopaste" flag to the pad.
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I am trying to place down some fiducials with a 40mil round copper
center with 88mills of clearance (from the center of the fiducial) and
80 mils of solder mask. I am doing it by using the following command
inside my footprint file.
Pad [-13188 -15000 -13188 -15000 4000 4800 800
On Thu, 2010-12-02 at 16:13 -0500, Bob Paddock wrote:
> Peter, while all of this sounds great, could we fix the collective
> problems that we have now first?
> To many of us PCB is used to ship products, preferably today.
Fixing problems is not always fun, especially if one is not really
sufferin
Bob Paddock wrote:
Rick, I got line breaks.
.
On Thu, Dec 2, 2010 at 3:02 PM, Peter Clifton wrote:
Just thought I'd write some of this down and put it out there. I've
spent some time recently thinking way into the future about the GUI /
usability for an advanced PCB editing program.
On Sat, 2010-12-04 at 11:15 +1100, Stephen Ecob wrote:
> hid/common/actions.c:269' <- Can't see this one myself.. there is no exit
> path out of that function which fails to free that allocation!
> hid/common/actions.c:46' <- Array of actions persistent over PCB's entire
> execution. Not a le
> I've looked at various commercial boards recently, and it would appear
> that many use negative layers to draw tracking. High power stuff,
> where practically everything is copper, just with some isolation
> between regions. The complexity of the polygons which make up these
> traces would b
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