On Sun, Jan 16, 2011 at 11:28 PM, wrote:
> Yes, I agree on this one. I think storing such modification date is just
> the wrong thing to do.
>
> ...
>
> I suggest we make this part of the file format optional, default turned
> off. (Feature request #1)
>
+1 agree, kill with fire, would do busine
On Mon, Jan 17, 2011 at 08:22:02AM +0100, Stephan Boettcher wrote:
> ge...@igor2.repo.hu writes:
>
> > If you edit one object, that won't ever move other objects around by
> > side effect. VCS systems I know depend on this feature. I think PCB
> > already provides this feature, keeping order of
Am 17.01.2011 01:10, schrieb Bob Paddock:
Is there a page on the wiki about how to use git specific to gEDA/PCB,
Like how to format patches etc.?
I think, http://geda.seul.org/wiki/geda:scm has the informations about that.
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ge...@igor2.repo.hu writes:
> If you edit one object, that won't ever move other objects around by
> side effect. VCS systems I know depend on this feature. I think PCB
> already provides this feature, keeping order of objects,
Not really. When you edit a line, it somehow gets thrown into an
e
Peter Clifton writes:
> On Sun, 2011-01-16 at 11:44 -0600, John Griessen wrote:
>> On 01/16/2011 11:32 AM, John Griessen wrote:
>> > So I don't see how that was a stopper, even without Bill's specific Altium
>> > experience.
>>
>> I meant Bob's
>
> I'm lost.. who is Bob?
You do not use a threa
It's well past time to realize that there is more to simulation
than Spice. A schematic should be able to be used with a
variety of simulators, and the netlister should take care of
the differences.
Symbols should not have anything specific to any output format.
This is difficult considerin
On Sun, 16 Jan 2011 20:20:32 -0600
John Griessen wrote:
> On 01/16/2011 08:07 PM, Kai-Martin Knaak wrote:
> > But no margin is
> > too little. Is there a way to set the size of the margin?
>
>
> Put something that prints along the edge of the page
> so that it goes int the unprintable space on
Hello Markus,
On Sun, Jan 16, 2011 at 10:11:31PM +0100, Markus Hitter wrote:
> Hi all,
>
> having run an open source electronics project with the intention of
> collaborative development for a few months now, the experience is less
> than inspiring. So I'm looking for opinions on how to do bett
On Jan 17, 2011, at 1:09 AM, al davis wrote:
> If simulation means Spice to you, you are 20 years behind.
> If Verilog means only digital to you, you are 20 years behind.
And yet, the infrastructure and community support for Verilog as more than a
digital tool are far poorer than for SPICE. Thu
On 01/16/2011 08:07 PM, Kai-Martin Knaak wrote:
But no margin is
too little. Is there a way to set the size of the margin?
Put something that prints along the edge of the page
so that it goes int the unprintable space on your printer.
Save that as a page border for use with your printer
and se
Hi.
The print dialog of gschem offers "Extents with margins" by default.
This margin is larger than necessary or my printer. But no margin is
too little. Is there a way to set the size of the margin? I couldn't
find "margin" in system-gschemrc.
---<)kaimartin(>---
--
Kai-Martin Knaak
Email: k..
> I'm lost.. who is Bob?
You're uncle?
(sorry, couldn't resist)
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On Mon, 2011-01-17 at 00:22 +0100, Kai-Martin Knaak wrote:
> Peter Clifton wrote:
>
> > Ok, I found the quote - it was in our "tips" for filing bugs. (gEDA and
> > PCB)
>
> Doh. I thought I had sifted through all the instances of sourceforge in
> the geda-wiki.
Indeed.. this was on our LP page
On Sun, 2011-01-16 at 11:44 -0600, John Griessen wrote:
> On 01/16/2011 11:32 AM, John Griessen wrote:
> > So I don't see how that was a stopper, even without Bill's specific Altium
> > experience.
>
> I meant Bob's
I'm lost.. who is Bob?
--
Peter Clifton
Electrical Engineering Division,
Engi
>> Ok, I found the quote - it was in our "tips" for filing bugs. (gEDA and
>> PCB)
>
> Doh. I thought I had sifted through all the instances of sourceforge in
> the geda-wiki.
It was on Launchpad actually.
Is there a page on the wiki about how to use git specific to gEDA/PCB,
Like how to format
al davis wrote:
>> Graphics information would be lost during the process.
> Yes .. you missed something. Verilog has a structural part too,
> which is well documented, has a published standard, and
> completely adequate for this.
Hmm, "structural" in the context of verilog always seemed to me
John Griessen wrote:
> You can attach it to an email, but better would be the geda wiki,
> http://www.geda.seul.org/wiki/geda:documentation#gnetlist_-_netlister,
>
> or ask for a user account for gedasymbols.org, where many tool scripts
> footprints and schematic symbols are gathered.
> http://ww
Peter Clifton wrote:
> Ok, I found the quote - it was in our "tips" for filing bugs. (gEDA and
> PCB)
Doh. I thought I had sifted through all the instances of sourceforge in
the geda-wiki.
--<)kaimartin(>---
--
Kai-Martin Knaak
Email: k...@familieknaak.de
Öffentlicher PGP-Schlüssel:
http://po
On Jan 17, 2011, at 6:53 AM, John Doty wrote:
> I use a slightly customized version of ngspice: it has the hspice semantics
> for the noise parameters used by TSMC. Unfortunately, the patch only works
> for the specific models TSMC provides: poor factoring of ngspice makes
> propagating that p
On Jan 16, 2011, at 1:52 AM, Florian E. Teply wrote:
> I seem to recall that some guys here use gEDA for chip design. John
> Doty comes to mind, but i think there are others too. I'd be interested
> in the workflow as i will have to make up some clever test chips in the
> next few years for PhD w
On 1/16/2011 4:11 PM, Markus Hitter wrote:
Hi all,
having run an open source electronics project with the intention of
collaborative development for a few months now, the experience is less
than inspiring. So I'm looking for opinions on how to do better.
http://reprap.org/wiki/Generation_7_E
Markus Hitter writes:
> Being more a mechanics and software guy, I'm astonished how things in
> the electronics world apparently work. Perhaps I'm exaggerating a bit.
>
> Is it even possible to do something in collaboration? I'd appreciate
> any answer.
In our lab we recently had very nice resul
On 01/16/2011 03:11 PM, Markus Hitter wrote:
Being more a mechanics and software guy, I'm astonished how things in the
electronics world apparently work. Perhaps I'm
exaggerating a bit.
Teams I've worked on set responsibilities and have time goals. I've not had
any free hardware collaboratio
Hi all,
having run an open source electronics project with the intention of
collaborative development for a few months now, the experience is
less than inspiring. So I'm looking for opinions on how to do better.
http://reprap.org/wiki/Generation_7_Electronics
http://github.com/Traumflug/Gen
On 01/16/2011 02:43 PM, Patrick Doyle wrote:
I'm somewhat confused by the twist things took here -- how does this
tie into gnucap? Are you requesting a plugin that would produce a
gschem schematic, given a gnucap internal representation?
Yes, I think that's one of the translator plugins Al wan
On Fri, Jan 14, 2011 at 8:59 PM, al davis wrote:
>> >> However we will also explore the possibility of publishing
>> >> the files for one of the Open ECAD packages such as gEDA.
>>
>> How would the conversion be performed?
>
> That's obvious. They are waiting for us to provide a conversion
> util
Oliver,
First, this looks really, really cool. Congratulations!
On Jan 16, 2011, at 4:04 PM, Oliver King-Smith wrote:
> I don't
> think it would be appropriate in its current form for distribution to
> the general public. It was written specifically for my needs in a
> quick and dirty fas
On Jan 15, 2011, at 1:42 AM, Peter Clifton wrote:
> I want to see all connectivity code move into libgeda, and
> flattening be optional.
Connectivity is precisely the kind of thing that should not be in libgeda. The
connectivity model depends on the application of the schematic. Right now, gEDA
On 01/16/2011 01:04 AM, Oliver King-Smith wrote:
It was written specifically for my needs in a
quick and dirty fashion. It also lacks any comments.
Having issued my disclaimers, I am happy to post it. How do I do that?
You can attach it to an email, but better would be the geda wiki,
On Sunday 16 January 2011 17:22:06 Peter Clifton wrote:
> On Sun, 2011-01-16 at 08:03 -0800, Colin D Bennett wrote:
> > On Sat, 15 Jan 2011 08:47:19 +
> >
> > Peter Clifton wrote:
> > > Are there any use-cases for invisible text which is not an
> > > attribute? Since it might exist already th
On 01/16/2011 11:32 AM, John Griessen wrote:
So I don't see how that was a stopper, even without Bill's specific Altium
experience.
I meant Bob's
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> https://bugs.launchpad.net/pcb/+filebug
>
> Which does not report as you quoted below. It is possible someone has
> fixed before I looked though.
Looks like it. You had to submit a summary and hit 'next' to get that
message. The message is now different:
pcb bug reporting guidelines:
You can
On 01/15/2011 06:32 AM, Bob Paddock wrote:
git HEAD rendering speed alone
would make it prohibitive.
I've been able to layout dense boards. The autorouter for digital wires after
the main power is laid out doesn't need rendering
So I don't see how that was a stopper, even without Bill's
On Sun, 2011-01-16 at 17:24 +, Peter Clifton wrote:
> On Sun, 2011-01-16 at 09:32 -0500, Bob Paddock wrote:
> > I wanted to submit a patch to PCB.
> >
> > Launchpad tells me to use the Source Forge tracker, which can't be
> > found on Source Forge anymore:
>
> Send me the link to the page whi
On Sun, 2011-01-16 at 09:32 -0500, Bob Paddock wrote:
> I wanted to submit a patch to PCB.
>
> Launchpad tells me to use the Source Forge tracker, which can't be
> found on Source Forge anymore:
Send me the link to the page which says that and I'll fix it. You want:
https://bugs.launchpad.net/pc
On Sun, 2011-01-16 at 08:03 -0800, Colin D Bennett wrote:
> On Sat, 15 Jan 2011 08:47:19 +
> Peter Clifton wrote:
>
> > Are there any use-cases for invisible text which is not an attribute?
> > Since it might exist already though - we MAY have to add an:
> > "Invisble [x]" option to the text
On 01/16/2011 10:09 AM, al davis wrote:
You are thinking of the original Verilog, as it was in its first
draft from Cadence over 20 years ago.
Heh! You have me dated Al. That's when I was using Cadence's Verilog-XL
the most. All I was getting at is the core meanings of verilog
are not proced
On Sat, 15 Jan 2011 08:47:19 +
Peter Clifton wrote:
> Are there any use-cases for invisible text which is not an attribute?
> Since it might exist already though - we MAY have to add an:
> "Invisble [x]" option to the text edit dialogue box.
I often include lines or even paragraphs of invisi
On Sunday 16 January 2011, John Griessen wrote:
> On 01/15/2011 10:36 PM, al davis wrote:
> > Unless I massively missed something, verilog is completely
> > procedural.
>
> Really verilog is all in parallel, not procedural code,
> unless you want to put some in with special features that
> are tri
On 01/15/2011 10:36 PM, al davis wrote:
Unless I massively missed something, verilog is completely
procedural.
Really verilog is all in parallel, not procedural code, unless you want to put
some
in with special features that are trickier to use than everyday verilog.
The basic statement of
I wanted to submit a patch to PCB.
Launchpad tells me to use the Source Forge tracker, which can't be
found on Source Forge anymore:
Error - The Tracker has been disabled for this group
Seems we have a case of circular instructions between the two sites right now.
http://pcb.gpleda.org/ ->
http
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