On 03/11/2011 10:51 AM, Levente Kovacs wrote:
On Thu, 10 Mar 2011 17:47:58 +
Could you please upload it to the tracker? It might get more attention.
I'd really see it checked into the HEAD. Every time I compile a new PCB, I have
to patch.
Browsing the source, I see that there is some moveme
On Thu, Mar 10, 2011 at 7:34 AM, Thomas Oldbury wrote:
> I am using an outline layer in PCB. It complains of DRC violations when
> the outline is too close to vias. Is it possible to get it to skip DRC
> on these?
>
>
Previous discussion: http://archives.seul.org/geda/user/Feb-2010/msg00209
On Fri, 11 Mar 2011 02:32:06 +0100
Kai-Martin Knaak wrote:
> Kovacs Levente wrote:
>
> > However, it is not a good idea to place vias close to the edge of
> > the board.
> Sometimes it may even be desired
> to have a plated hole on the center of the outline. The result is
> a metalized cylindri
On Thu, 10 Mar 2011 17:47:58 +
Ineiev wrote:
> Thank you! it would be nice if someone added corresponding bits
> of documentation to the patch.
Could you please upload it to the tracker? It might get more attention.
I'd really see it checked into the HEAD. Every time I compile a new PCB, I
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