Stephen Williams <[EMAIL PROTECTED]> writes:
> An approximation of the answer you are looking for is to look
> in the ivl_target.h header file. This will show all the different
> types of gates might be passed to the edif code generator. Of
> course, not all those gates are necessarily actually ge
Does anybody know where I might find a comprehensive list of the EDIF
cell types emitted by icarus' synthesis back-end? I'd like to try to
get an idea of where the finish line is in terms of supporting all the
cell types it might throw at my stuff.
I've got the router in pretty good shape at thi
Please bear in mind that this is only an 8-bit ripple-carry adder, and
the tools are still quite crude, but I believe we now have the
first-ever instance of a design being taken through a 100% open-source
flow, all the way from verilog to blinking lights on a programmed device.
Details are here:
Stephen Williams <[EMAIL PROTECTED]> writes:
>> One difficulty, though: the primitive cells that iverilog emits are
>> pretty complex. Is there any way to ask it to break down multipliers
>> and adders into stuff no larger than a LUT4?
> The reason it generates at that level is that in some case
Stephen Williams <[EMAIL PROTECTED]> writes:
> The v0.8 releases of Icarus Verilog have decent synthesis. The
> synthesis is not at all Xilinx specific, but the code generators
> are. But they needn't be. The FPGA target generates EDIF, so if
> your intermediate form takes EDIF, the way to move fo
Stephen Williams <[EMAIL PROTECTED]> writes:
> The v0.8 releases of Icarus Verilog have decent synthesis. The
> synthesis is not at all Xilinx specific, but the code generators
> are. But they needn't be. The FPGA target generates EDIF, so if
> your intermediate form takes EDIF, the way to move fo
So, now that the abits work is published [1] I plan on turning my
attention to "connecting the dots", so to speak.
I've pretty much resigned myself to the fact that I'll have to
implement PAR by hand (VPR has licensing issues, and there are far
more architecture-portable algorithms now anyways [2
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