17, 2011, at 6:57 AM, George M. Gallant, Jr. wrote:
I have created a symbol for the TI ADS1298. It has multiple power pins,
DVdd, DVss, ADvv,& AVss. For test purposes, I declared 1 of the pins as
a net.
Loadiing the schematic gives:
Read garbage in [ads1298-1.sym] :
net=AVdd:21
<<
I&
I have created a symbol for the TI ADS1298. It has multiple power pins,
DVdd, DVss, ADvv, & AVss. For test purposes, I declared 1 of the pins as
a net.
Loadiing the schematic gives:
Read garbage in [ads1298-1.sym] :
>>
net=AVdd:21
<<
Is there a tutorial available that describes the proper synta
If the new system is anything like this list, you should expect
a significant slowdown as the CPUs argue amongst themselves
as to who gets to do what, when and how not to do something.
I have not seen a significant advantage to single process geda tools
execution. I suspect that some of the backe
How about an external filter utility that could remove (with
appropriate message) the offending line segments.
George
On 01/23/2011 10:01 AM, Peter Clifton wrote:
On Sun, 2011-01-23 at 23:52 +0900, Andrzej wrote:
Krzysztof,
I'd like to get opinions on the drawing of visual cues (end
SeeedStudio - low price for their standard size boards. Slow shipping to US
GoldPheonix - good price for the 100 in-sq. Same mfg as sparkfun batchpcb
DorborPDX - batch pcb service but about 2 panels per month.
George
On 01/21/2011 01:05 PM, yamazakir2 wrote:
Hi all,
I have been using 4pcb f
Is there any documentation on how to use "polygon hole"?
George
On 01/17/2011 03:19 PM, Kai-Martin Knaak wrote:
George M. Gallant, Jr. wrote:
I would like to embed a polygon within a polygon keeping
clearance between the inner an outer. So far I have succeeded
by creating
On 01/18/2011 01:13 PM, Peter Clifton wrote:
On Tue, 2011-01-18 at 11:56 -0500, George M. Gallant, Jr. wrote:
See the attached screenshot.
Mailing list has scrapped the attachment I think.
I don't think there is a better technique for now. Perhaps you could
explain what the polygons a
On 01/17/2011 03:19 PM, Kai-Martin Knaak wrote:
George M. Gallant, Jr. wrote:
I would like to embed a polygon within a polygon keeping
clearance between the inner an outer. So far I have succeeded
by creating the inner shape first and then applying multiple
shapes around it.
(..snip..)
Is
Peter,
A clearance of 2731 passes, 2732 crashes. Attached is a more minimalist
file.
What is required to run the OpenGL port?
George
On 01/18/2011 11:31 AM, Peter Clifton wrote:
On Tue, 2011-01-18 at 11:17 -0500, George M. Gallant, Jr. wrote:
Peter,
I just redid the git, rebuilt pcb, same
Peter,
I just redid the git, rebuilt pcb, same results.
[ggallant@firefly pcb]$ git rev-parse HEAD
13de8601a39f2ed2a18aca814598f3ebe17ff506
George
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-
Peter,
I got the git development version about 12 hours ago. I would like the
embedded polygons.
George
On 01/18/2011 10:47 AM, Peter Clifton wrote:
On Tue, 2011-01-18 at 09:32 -0500, George M. Gallant, Jr. wrote:
Peter,
I started to remove items until it succeeded. Removed all trace&
rectangle on the empty ground layer
segfaults.
System is up to date 64-bit Fedora 13.
George
On 01/17/2011 03:19 PM, Kai-Martin Knaak wrote:
George M. Gallant, Jr. wrote:
I would like to embed a polygon within a polygon keeping
clearance between the inner an outer. So far I have succeeded
by
I would like to embed a polygon within a polygon keeping
clearance between the inner an outer. So far I have succeeded
by creating the inner shape first and then applying multiple
shapes around it.
I also drew box around the inner using standard trace.
The intent is to create an isolated ground
Ran without any user intervention on Fedora 13. Installed Ruby
some time ago without knowing if I would ever use it.
Depending on the window sizing, either the top/bottom horizontal
line heights or the left/right vertical line widths do not display fully.
George
On 12/26/2010 08:48 AM, Stefan S
The gschem "Add Attribute" defaults to "Show Name & Value". Is there
a user selectable option to default to "Show Value Only"?
George
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
I am looking for the footprint for a 2 x 4 2mm surface mount header.
Geoge
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Not at all. Just to goad you into a further negative rant on how
a free product, created by volunteers bothers you.
George
On 12/13/2010 08:57 PM, timecop wrote:
Why do you bother to subscribe to this list? Its obvious that $0.02 is
worth more than your opinions.
Why do you bother replying?
Is
On 12/13/2010 08:23 PM, timecop wrote:
Another option, that may not be acceptable to all, is that in the UK
RS& Farnell both recently acquired small PCB development
companies(DesignSpark& eagle respectively). The intention being the
companies adopt the free tool which integrates easily with
10:34 -0500, George M. Gallant, Jr. wrote:
I am looking to make a trapezoid shaped pad for an inductor. So far, I
created
a rectangular pad and drew lines on the surface to create the shape. Is
there
a better way as I would like to reuse the pad shape.
No good way at present. Within a footprint
I am looking to make a trapezoid shaped pad for an inductor. So far, I
created
a rectangular pad and drew lines on the surface to create the shape. Is
there
a better way as I would like to reuse the pad shape.
George
___
geda-user mailing list
geda-
Well that was interesting. The tracks->Miter made it look very sloppy
and the completely hung PCB. Using version 20100929.
George
On 12/05/2010 03:40 PM, Stephen Ecob wrote:
I don't think chamfering is available. Other related features are
available though:
Mitering is available from Connects-
Is there a method to automatically apply chamfer to an entire board?
George
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Is there an option to show pin numbers on non-polarized resistors/caps
etc in gschem?
George
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Peter,
It is currently working. I missed the requirement to use:
"print-colormap-lightbg"
George
On 09/01/2010 04:13 PM, Peter Clifton wrote:
On Mon, 2010-08-30 at 22:26 -0400, George M. Gallant, Jr. wrote:
I am having difficulty in generating ps files from the
comand line wi
I am having difficulty in generating ps files from the
comand line with a light background. This is a infrequent
event for me and I have entries in Makefiles. Last successfully
used over a year ago and a different version of gschem.
The GUI option works as expected.
George
_
I have a couple of hopefully easy questions:
1. Is there a tutorial on how to use hierarchy in gschem/pcb?
Just finished a board with 8 identical analog circuits. It
would have been nice to draw one and let the tools do the
rest.
2. What is the function of "rubberend" in PCB?
Thank
It is very generous of you to provide transportation and accommodations.
On 07/01/2010 01:04 AM, DJ Delorie wrote:
In October I'm going to be giving a presentation at a conference, and
I'll be talking about open source EDA. Part of the deal is I get a
booth in the trade show area. Since I have
Matthew,
I cut & pasted you test. Followed the instruction presented by
gsch2pcb. No problem.
BTW, I have never used gsch2pcb before and felt this was a good
opportunity to
try it out.
George
On 06/10/2010 03:34 PM, Matthew Lai wrote:
Hi,
I've posted this on the b
I recall turning off the email options for news list update. As I havn't
received any I guess its working. How to I turn it back on?
George
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Stefan,
I just received 5 different double sided boards with a combination of SMD and
thru-hole devices. Schematic with GSCHEM and layout with PCB.
For jumpers I create a third layer. You then use via's to get to this dummy
layer and trace to simulate the jumper. Just don't send the board sh
For a little more money (~$3.00) take a look at the Nordic Semiconductor reference
design for the NRF24L01 radio transceiver. Lots of small parts and you get a functional
2.4GHz radio when done. I have some commercial modules ($14.95 from Spark Fun)
so the acid test would be easy to setup.
G
Peter,
I changed the name to xSO-28, SOIC-28 and they behaved correctly. Thanks for duplicating
my results.
George
On Sun, 2006-08-06 at 15:49 +0100, Peter C.J. Clifton wrote:
On Aug 6 2006, George M. Gallant, Jr. wrote:
>Yesterday I posted a message regarding a failure in gsch2pcb w
Yesterday I posted a message regarding a failure in gsch2pcb when the footprint
contained the string "SO-28". It seems that any footprint beginning with "SO-"
will fail.
Attached are my test schematic and project files. I would appreciate feedback.
George
schematics so28.sch
output-name so2
I created a footprint called SO-28. I then ran g2ch2pcb on a small test.sch file and it goes into
an finite loop generating pads with the following error messages:
stdin:5: /usr/bin/m4: Bad _expression_ in eval: (1028* - /2)/100
stdin:5: /usr/bin/m4: Bad _expression_ in eval: (1028* - /2)/100
John,
You forget that DJ has to pay a premium to have the parts delivered up his driveway.
George
On Fri, 2006-08-04 at 20:12 -0400, John Luciani wrote:
On 8/4/06, DJ Delorie <[EMAIL PROTECTED]> wrote:
> Besides, at that price, all you get is some pF caps and a couple of
> inverter/buffer
Same tool, same name, different purpose. Keeps me in a constant state of confussion.
Now stuck on something that is probably trivial. gsch2pcb finds my new footprints but
pcb doesn't.
George
On Fri, 2006-08-04 at 13:56 -0400, Stuart Brorson wrote:
On Fri, 4 Aug 2006, George M. Ga
Many of the symbols contain an entry in the form of "device=xxx". However these entries do
not appear to in the ".sch" file when the symbol gets added to the schematic. We can manually
assign a device attribute which appear to have the same syntax.
Am I missing the process of importing attribu
casual (or worse) reader wants to delve into.
George
On Fri, 2006-08-04 at 12:07 -0400, Stuart Brorson wrote:
On Fri, 4 Aug 2006, George M. Gallant, Jr. wrote:
> Thanks for the replies. Ten seconds of clicking replaced 1/2 hour of
> work.
That's why I wrote gattrib in the first pla
Thanks for the replies. Ten seconds of clicking replaced 1/2 hour of work.
George
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
I am try to generate a BOM for a number of small projects that use
common components. Using gattrib is a great help. However, when
I go back to gschem all my "helpfull" attributes clutter the schematic.
1. Is there a user modifiable config somewhere?
2. How do I preset the column order width i
Stuart,
The wiki references both $HOME/.geda and $HOME/.gEDA.
George
On Thu, 2006-08-03 at 17:10 -0400, Stuart Brorson wrote:
The whole issue of the gafrc file is a FAQ:
http://geda.seul.org/wiki/geda:usage#what_are_the_names_and_locations_of_the_rc_files_used_with_geda_gaf_applications
Tom,
I don't have an answer, just a question as I am in a similiar snafu.
Where does gafrc belong. I am having better results putting it in
$HOME.
Georhe
On Thu, 2006-08-03 at 11:53 -0700, User Tomdean wrote:
I am having problems with hiearchy.
I want to have a hiearchy with an inout bus
I have been playing with creating footprints to help automate the
interaction of gschem and pcb. So far I have been able to assign
value attributes in gschem, create a project file, and generate a
pcb from gschem2pcb.
Once in pcb all the elements are pack in to top left. Disperse, optimize
rat
Stuart,
I thinks its an improper text string. There were additional junk chars that did not show up in the
paste buffer.
George
On Tue, 2006-08-01 at 15:02 -0400, Stuart Brorson wrote:
> Stuart,
>
> Built successfully. One error message:
>
> ./installer.exe:485: GtkWarning: gtk_text_buffer
Stuart,
Built successfully. One error message:
./installer.exe:485: GtkWarning: gtk_text_buffer_emit_insert: assertion `g_utf8_validate (text, len, NULL)' failed
\u(
Last night I installed xwWindows. I had two copies of the install CD and burned
the wrong one yesterday.
George
On Tu
Stuart,
Machine is not portable. This Thurs is NEMES and the speaker is a very accomplished blacksmith.
The make fails but the installer.exe continues to run at 100% cpu utilization.
The Install.log is 1.5MB. Attached is the tail end with error.
George
make[1]: Leaving directory `/home1/g
orge --
>>
>> If all you want is GSpiceUI, the easiest thing to do is grab teh
>> source tarballs off the CD or off the gEDA website and build them by
>> hand.
>>
>> Stuart
>>
>>
>>
>>
>> On Mon, 31 Jul 2006, George M. Gallant, Jr. wr
ource tarballs off the CD or off the gEDA website and build them by
hand.
Stuart
On Mon, 31 Jul 2006, George M. Gallant, Jr. wrote:
> Stuart,
>
> Copied cd to home dir and running from there. Is there a way to install
> just the gspiceui?
>
> George
>
> On Mon, 2006-07-31 a
er magical incantation works for you)
2. Cd to your home directory and run the CD from there:
cd ~
/media/cdrom/installer --log
This will drop the Install.log file into your local directory. Then
you can examine it and/or send it to me.
Stuart
On Mon, 31 Jul 2006, George M. Gallant, Jr. wrote:
l.log file.
Stuart
On Mon, 31 Jul 2006, George M. Gallant, Jr. wrote:
> Stuart,
>
> I am hung while installing the 7/30 iso. Installing on a slow dual cpu
> system. One cpu
> is 100% busy in install.exe. No other jobs running. Last log message
> complained about
> unable to
Stuart,
I am hung while installing the 7/30 iso. Installing on a slow dual cpu system. One cpu
is 100% busy in install.exe. No other jobs running. Last log message complained about
unable to install gspiceui with unresolved symbols starting with "xw".
Also just got a page of junk after the fo
Thanks. Built without error. However, I still think that the cvs (or any other release
mechanism) should build without intervention.
George
On Mon, 2006-07-31 at 11:13 -0400, DJ Delorie wrote:
> Take a look at README.cvs which gives specific instructions about
> tracking cvs sources. In p
DJ,
The only log file is config.log.
Restarted from scratch:
rm -rf pcb
cvs -d:pserver:[EMAIL PROTECTED]:/cvsroot/pcb login
cvs -d:pserver:[EMAIL PROTECTED]:/cvsroot/pcb co pcb
cd pcb
./configure
make
The following is the last few lines of the make output
George
Ma
Executing make from the top level fails without these files. I copied them from 20060422
to get past the problem. Either they are needed or the make file needs reflect the current
condition.
George
On Mon, 2006-07-31 at 10:08 -0400, DJ Delorie wrote:
> > puller.png & thermal.png appear to b
puller.png & thermal.png appear to be missing in cvs.
George
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Makes sense. First thing I try fails. Am rebuilding now from CVS and lesstik. gtk
repaint is painfully slow on my system.
George
On Fri, 2006-07-28 at 20:06 -0400, DJ Delorie wrote:
> As a side note, what happened to the 'c' keystroke to center the
> design?
When we moved the GUI-specific
Thanks. Updated pcb to 20060422 and the "-x" worked. As a side note, what
happened to the 'c' keystroke to center the design?
George
George
On Fri, 2006-07-28 at 00:34 -0400, Dan McMahill wrote:
George M. Gallant, Jr. wrote:
> I am looking for a script file to pr
I am looking for a script file to print a pcb file. Ideally it could be embedded in a Makefile
to help automate the packaging of files that get set to the fab shops. Some shops spec
holes as raw drill size while others spec the finished plated size so I would like to create
my designs using one
Being the proud owner of a generic Staples "pouch laminating heater-roller" I can only state that
I wished I needed it for its intended purpose. The only success I had was with single sided 0.031
panels. Getting more heat and less pressure might improve the results. I use the blue Press-n-Peel
What is "additive conductive ink"?
George
On Wed, 2006-07-26 at 23:07 -0500, John Griessen wrote:
Yep.
Speed of getting a new rev. is about the only motivation
with those prices George put out from the per square inch shops.
After I get my prototype iterating done and the design/test proc
www.futurelec.com has a $1.50 per square inch no frills + $15.00 setup.
www.goldphoenixpcb.biz has a 155 per square inch for $90.00.
www.sparkfun.com has a $2.50 per square inch plus setup.
George
On Wed, 2006-07-26 at 16:07 -0700, Taylor Jones wrote:
On 7/26/06, Dan McMahill <[EMAIL PR
till blank.
Using the gEDA tools has greatly enhanced my ability to deliver prototype boards to
customers as well as one of a kind home project boards.
George
On Wed, 2006-07-26 at 08:14 -0400, Dan McMahill wrote:
George M. Gallant, Jr. wrote:
> I do homebrew image transfer boards with gsc
I need to take 6 small pcb's and create a single panel (I'm cheap).
Last time I used the brute force of:
1. load the pcb file
2. Create a symbol of the individual design
3. Cut, paste & rotate.
This time I am open to suggestions.
Thanks,
George
__
Stuart,
Do these "spare seats" have any relation to "spare gates"?
Do to float when when the driver is disconnected or are
they pulled to ground?
George
On Fri, 2006-07-21 at 08:23 -0400, Stuart Brorson wrote:
Just a note --
I have two spare seats in my car. If anybody in the Boston are
I want to convert a small thru-hole design to a surface mount. Started
with a netlist and placed ic, 603 & 1206 parts from geda lib on board.
It appears that the parts are all on the component side for viewing but
solder side for connectivity. Auto route works.
Using pcb 20050609.
Time for a
I do homebrew image transfer boards with gschem and pcb. 15 mil trace expands to
about 20 mil under heat and pressure. 1/4 oz boards are great for etch time but the
underlying glass fabric causes visible waves in the transfered toner.
George
On Wed, 2006-07-19 at 22:10 -0400, DJ Delorie wrot
Is there a method to assign the device type in gschem such that pcb will fetch
the correct type? John suggested creating a separate part id (John also likes to
create his own footprints). At a minimum, I think gschem and pcb should default
to the same labeling scheme and as I don't care which p
John,
EMACS and PCB. A match made in heaven/hell!
George
On Mon, 2006-07-10 at 08:37 -0400, John Luciani wrote:
On 7/9/06, George M. Gallant, Jr. <[EMAIL PROTECTED]> wrote:
>
> John,
>
> Thanks. My next question was how to migrate the proto from thru hole
> to SMT.
, John Luciani wrote:
On 7/9/06, George M. Gallant, Jr. <[EMAIL PROTECTED]> wrote:
>
> I think there is a difference in pin assignments on the 2N3906
> parts between GSCHEM and PCB.
>
> E BC
> PCB123
> GSCHEM
I think there is a difference in pin assignments on the 2N3906
parts between GSCHEM and PCB.
E B C
PCB 1 2 3
GSCHEM 3 2 1
I am not very good at transistors and the resultant circuit
has some strange behavior (not all bad). I notice
70 matches
Mail list logo
