We have some local netlisters we used, and I would like to add
something to the gnetlistrc file to allow gnetlist to find them. We
tried:
(scheme-directory "/path/to/scheme")
but that causes it to not find the files in /usr/share/gEDA/scheme
which are still needed. Is there a way to specify m
On Sat, Nov 14, 2009 at 7:01 AM, DJ Delorie wrote:
>
> Stack issues?
>
> http://www.geda.seul.org/wiki/geda:faq-gnetlist
This has been happening for years. Why not just make the default
stack bigger and avoid the problem in the first place?
Matt
__
On Wed, Sep 30, 2009 at 11:35 AM, Peter TB Brett wrote:
> On Wednesday 30 September 2009 16:37:52 evan foss wrote:
>> Hi,
>> I just tried to generate color Postscript output in both
>> 1.5.2.20090328 and 1.5.4.20090830 and found that it won't work. Is
>> anyone else having this problem? My gschemr
On Wed, Sep 30, 2009 at 10:07 AM, Stefan Salewski wrote:
> On Wed, 2009-09-30 at 15:37 +, evan foss wrote:
>> Hi,
>> I just tried to generate color Postscript output in both
>> 1.5.2.20090328 and 1.5.4.20090830 and found that it won't work. Is
>> anyone else having this problem? My gschemrc fi
See http://gnuradio.org/trac/browser/usrp-hw/trunk/sym/sd_mmc.sym
No footprint, though.
Matt
On Wed, Mar 18, 2009 at 11:14 PM, DJ Delorie wrote:
>
> Anyone done any sd-card designs? Looking for symbols, footprints,
> connector recommendations, schematics, anything I can leech off you :-)
>
> N
One other bug -- if I edit a file, close it without saving changes,
and then try to edit another file, it crashes with:
gEDA/gschem version 1.4.3.20081231
gEDA/gschem comes with ABSOLUTELY NO WARRANTY; see COPYING for more details.
This is free software, and you are welcome to redistribute it un
On Tue, Feb 10, 2009 at 4:23 PM, Stephen Williams wrote:
> Matt Ettus wrote:
>> In some Xilinx models, they make instantiations like this:
>>
>> block instance(ports);
>> defparam instance.param=VALUE
>>
>>
>> This normally works ok. The problem is
> Depending on the order of the schematics on the gnetlist line, you will
> get a different net renamed (DVDD_FPGA -> Vcco2 or DVDD_FPGA -> Vcco3).
>
> This is most certainly a bug in gnetlist and probably has been there
> since the beginning of time. I am guessing it worked in the past due
> to s
On Mon, Feb 16, 2009 at 6:05 PM, Ales Hvezda wrote:
> Hi Matt,
>
>>In many of my schematics, I would have multiple power symbols, and
>>when I wanted them to be the same, I just connected them. However,
>>that no longer works! The netlister is making them separate nets.
>
>I cannot seem
In many of my schematics, I would have multiple power symbols, and
when I wanted them to be the same, I just connected them. However,
that no longer works! The netlister is making them separate nets.
Was this intentional?
Matt
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Thanks! That fixed it.
Matt
On Tue, Feb 10, 2009 at 1:32 PM, Stefan Salewski wrote:
> Am Dienstag, den 10.02.2009, 12:06 -0800 schrieb Matt Ettus:
>> In my gafrc file in the current directory, I have the line:
>>
>> (paper-size 17.0 11.0) ; tabloid
>>
>
> Fo
In my gafrc file in the current directory, I have the line:
(paper-size 17.0 11.0) ; tabloid
However, this is ignored by gschem even though the status window
reports "read local gafrc". This behavior turned up in 20081231 from
Fedora 10, but was ok in 20081220 from Fedora 8.
Any ideas? Its no
In some Xilinx models, they make instantiations like this:
block instance(ports);
defparam instance.param=VALUE
This normally works ok. The problem is that inside the block,
generate statements are being used which are dependent on the value of
the parameter. What appears to be happening is th
If you put pins on either the top or bottom of a symbol, tragesym
moves the name around and changes the positioning. However, this is
only necessary if pins are on top, and the logic should ignore pins on
the bottom. The following patch:
$ diff /usr/bin/tragesym tragesym
300c300
< if numpbot
The problem is that there are 2 kinds of SOIC -- wide and narrow.
Matt
On Sun, Jan 18, 2009 at 1:56 PM, Bdale Garbee wrote:
> On Sun, 2009-01-18 at 16:38 -0500, Rob Butts wrote:
>> I looked in PCB; is the 8 pin SOIC called SO8?
>
> That's one of them. Be careful, though, experience has shown t
On Tue, Dec 30, 2008 at 2:26 PM, Peter TB Brett wrote:
> On Sunday 04 January 2009 22:25:23 Matt Ettus wrote:
>> I am using the 20081220 RPMs on Fedora 8. I have been seeing a lot of
>> new bugs lately --
>>
>
> All the patches that have gone into the 1.4.x stable ser
I am using the 20081220 RPMs on Fedora 8. I have been seeing a lot of
new bugs lately --
If you hit "fq" (file-quit) with a bunch of pages open, some of
which are unsaved, and choose cancel or don't save, sometimes gschem
crashes
While editing a symbol, hitting "undo" will undo ALL changes,
I often use text on my schematic pages in the form of a table, so I
use tabs to make columns. On the screen, these show up fine, but when
printed, the tabs come out as capital Y's with umlauts on them. Is
there some way to fix this?
Thanks,
Matt
___
On Jan 25, 2008 7:38 AM, Günter Dannoritzer <[EMAIL PROTECTED]> wrote:
> Well, I will be honest with you. Trying to figure out truss/teal I am
> still finding some other problems of the software itself that makes me
> not succeed using it. So for now I can live with using it with the
> stable versi
Does anyone have a model for an SD or MMC card? Preferably in
Verilog, but VHDL would be ok too. I am developing something which
will talk to the cards, so a model of a card would be very helpful.
Thanks,
Matt
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I found this package to do sin and cos from PLI:
http://www.chris.spear.net/pli/math.htm
But I can't get it to run with Icarus. I get the following errors
when I compile:
[EMAIL PROTECTED] math]$ vvp -M. -mmath math
math: no vlog_startup_routines
$exp: This task not defined by any modules. I
Anybody know of an RS232 to TTL level translator board or kit that
comes complete? Possibly in a box? I know its easy to make, but I
need a bunch and fast. No time to sit down and solder max232s myself.
Thanks,
Matt
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There is a Xilinx FPGA in a BGA package with 484 pins spaced at 0.8
mm. I need to mount it at 45 degrees. Is this a bad idea? Will I
run into manufacturing issues? And can PCB put components down at 45
degrees?
Thanks,
Matt
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Icarus in the git repository has made a lot of progress lately,
especially in handling 2 dimensional regs and wires, and generate
statements. I use the latest git version on linux, but I work with
some people who use it on Windows. Is anyone making windows binaries
from recent git versions?
Matt
Many of the netlist backends are implemented with recursive functions,
so large schematics cause this. The real solution is to rewrite them
as properly tail-recursive. The interim solution is to adjust the
stack size to be much bigger:
http://archives.seul.org/geda/dev/Jan-2002/msg00024.html
Ma
Another update...
It seems like the problem is too many signals If I comment out a pair
of the 32-bit wide ports then everything is ok. Doesn't matter which
ones, as long as I remove 2 32-bit buses.
Matt
On 6/18/07, Matt Ettus <[EMAIL PROTECTED]> wrote:
> An update on this --
On 6/18/07, Matt Ettus <[EMAIL PROTECTED]> wrote:
> Got another one for you. I am now using the latest git version as of
> this morning. I get the following assertion when trying to compile
> the attached files. They are short, but I put them in a tarball. The
> code shouldn&#x
Got another one for you. I am now using the latest git version as of
this morning. I get the following assertion when trying to compile
the attached files. They are short, but I put them in a tarball. The
code shouldn't do anything useful yet, but I believe it is
syntactically correct. The co
On 6/17/07, Stephen Williams <[EMAIL PROTECTED]> wrote:
>
> Your example below is within the skills of Icarus Verilog, but
> there was a very recent fix for exactly this problem. According to
> my git logs, it was committed 6/11/2007, which is *after* the very
> last snapshot. So try the current gi
I have the following code in a module:
genvari;
generate
for (i=0;i<32;i=i+1)
begin : gen_srl16
SRL16E
srl16e(.Q(dataout[i]),
.A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
.CE(write),.CLK(clk),.D(datain[i]));
I get the following errors when trying to compile a dual-ported ram in
icarus. I'm sure my syntax must be bad somewhere, but I can't see
where.
duram.v:31: internal error: The indices are not constant for array ``ram''.
duram.v:36: error: Could not find variable ``ram'' in ``duram''
duram.v:37:
I wrote a CORDIC which is scalable in number of stages and bit widths
throughout. It is verilog, and GPL'ed, as part of the USRP. You can
get the code out of the GNU Radio SVN from http://gnuradio.org/trac
Matt
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If I put tabs in text in a schematic, it shows up fine on the screen.
However, it prints funny -- the Tabs come out as Y's with 2 dots on
top.
Is there a fix for this?
Thanks,
Matt
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When I select a piece of silkscreen text and choose "Change Size of
Selected Object" and "Increment text by 10" or "decrement text by 10"
it doesn't change text size. I'm using the gtk-hid.
Matt
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htt
At some point the 0603 footprint in the CVS version of PCB lost the
silkscreen rectangle around it. Is there any reason it went away?
Was this intentional?
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protoexpress auto-adds copper thieving, which would mess up my
isolation gaps (I've emailed them asking about it).
What is "copper thieving"?
I wanted to go
with pcbex, but they're closed for the next two weeks. Other vendors
on my list are: pcbfabexpress (25 mil minimum SMT pitch) and pcbpoo
When using the gtk-hid for PCB, I see some strange behaviors every now
and then. For example, usually when I press "z", it usually zooms.
However, sometimes it gives me the message "click on focus for zoom"
or something like that, forcing me to either click, or to press "z"
for a second time. It
If you run "gsymupdate *", it will not check what is a symbol, and
will destroy other files and even directories. Luckily, it makes
backups, but it is still very messy. Simply checking that something
is not a directory would be nice.
Matt
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The Ubuntu gEDA packages are from last year, but they seem to be the
only option. They segfault on page closes for me, and even more often
for a friend. Anybody know why? Are there newer packages available
somewhere?
Thanks,
Matt
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Does anyone have gschem symbols they've created for Spartan 3s in the
320 or 456 pin packages?
Thanks,
Matt
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Does anybody know how I could perform the equivalent of $realtobits in Python?
Thanks,
Matt
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