ownload but remember its cygwin, not native windows.
That puts some people off, although with the import schematics feature
in pcb it's now possible to pretty well avoid the command line (if
you're careful with paths).
--
Peter Baxendale
__
gt; >
> > Like I mentioned before -- I'll investigate next week.
>
> Any findings?
>
>
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p-m4" in
> the
> project file. CMD-window output contains a backtrace. Unfortunately,
> windows is unable to copy-paste tjhis text. So we made a screenshot
> --
> see attachment
--
----
Peter Baxenda
mm instead of mils
Yes indeed,
pcb -x bom --xyfile foo.txt foo.pcb
does the trick. Thanks! I'd forgotten the --help and it hadn't occurred
to me that it would be a bom option.
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Is it possible to generate a centroid file from pcb for use by a pick
and place machine? The pcb manual and various old postings seem to
suggest you can, but I can't see how to do it.
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Peter Baxendale
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geda
On Wed, 2009-06-17 at 11:07 +, Kai-Martin Knaak wrote:
> Peter Baxendale is almnost there with his cygwin port. He does it once a
> year to serve the local students. For whoever missed the announcement
> last month: I put the latest port by Peter along with the latest direct
>
ing it all in. It just gives them a taster for what might be
possible using simulation.
Sorry if I've started a swcad/gnucap/windows/linux war. I just happened
to have something I annually spend some time putting together and
suddenly realised that it might be useful to someone else.
--
ced - something that's been on my summer list of things to do for
the past few years.
--
--------
Peter Baxendale University of Durham
peter.baxend...@durham.ac.uk School of Engin
ally a pretty tough test to pass...
--
----
Peter Baxendale University of Durham
peter.baxend...@durham.ac.uk School of Engineering
tel +44 191 33 42492 South Road
fax +44 191 33 42408 Durham DH1 3LE
is attached or unattached?
Is this just a case of documentation lagging development, or am I
missing something?
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Peter Baxendale <[EMAIL PROTECTED]>
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> o_update_component(), but that doesn't sound to be the same code-path
> as
> you're exercising here.
>
> Best wishes,
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8-02-07 at 10:45 -0500, Ales Hvezda wrote:
> The slot/pinseq renumbering change manifested itself in this fashion,
> but I thought that fix was in 1.3.1.
>
> Either way, please upgrade to 1.4.0 and let us know if this bug is in
> there as well for you.
>
> -Ales
--
Pe
d the pin numbers now change as they should. Seems to be a
problem with any slotted symbol you've just inserted - have to save,
exit and restart before the pin numbers display properly.
Is this a known bug?
--
Peter Baxendale <[EMAIL PROTECTED]>
etermine which CAD program that
> has been used to generate these gerber files? It usually says in the top
> of the file after some G04 remark command.
>
> Regards,
> /Stefan
>
--
Peter Baxendale <[EMAIL PROTECTED]>
__
Wow, that was quick! Hate to think what that kind of service would cost
commercially. Many thanks!
On Thu, 2008-01-24 at 10:59 +0100, Stefan Petersen wrote:
> Peter Baxendale wrote:
> > Hi gerbv people,
> >
> > Just posted a gerbv 2.0.0 "feature" to the gerbv
w lines and the
problem seems to relate to when circular interpolation should revert to
linear. All the other viewers I've tried (3 of them) show as per
Nordic's design, gerbv doesn't. Of course, I can see you might argue
that the others are all wrong...
--
Pet
included in the spice netlist.
Also make sure the pinseq attributes of each pin in your opamp symbol
match the order of the parameters to your spice model. In my
experience the gschem opamp symbols usually need changing.
--
Peter Baxendale <[EMAIL PROTECTED]>
___
:
> >
> > CFLAGS='m32" ./configure --with-hid=gtk
> >
> > however a subsequent "make" command responded as though "configure" had
> > not completed. In the end I had to go back to pcb-20070208.
>
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Peter Baxendale <[EMAIL P
ed out had newlib/keystone missing from
configure.ac, which stops the build.
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Peter Baxendale <[EMAIL PROTECTED]>
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ia.seul.org
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
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n pcb checked out from cvs today. I get a similar
message in config.log for the other Makefiles as well, and make install
fails because it tries to install to /pcb (ie it really does ignore
datarootdir).
I've a feeling I'm doing something daft, but I can't see what. Be
grateful for an
ess info on the top level schematic.
On Thu, 2007-07-19 at 10:06 +0100, Peter Baxendale wrote:
> OK, thanks for the response. Attached is a very simple hierarchical
> design. The .pcb and .net files were generated by "gsch2pcb --skip-m4".
> You can see the U?-? in the .net file
OK, thanks for the response. Attached is a very simple hierarchical
design. The .pcb and .net files were generated by "gsch2pcb --skip-m4".
You can see the U?-? in the .net file.
On Wed, 2007-07-18 at 07:11 -0400, John Luciani wrote:
> On 7/18/07, Peter Baxendale <[EMAIL PROTECTE
el schematic?
>
>
> Steve Meier
>
>
> On Tue, 2007-07-17 at 17:04 +0100, Peter Baxendale wrote:
> > Been experimenting with hierarchical design with gschem. When I generate
> > the netlist using gsch2pcb I
SW1-2 U?-?
I'd much appreciate it if someone could tell me where I'm going wrong.
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d mingw
- for instance on those issues of path specifications - and there seems
little documentation around. If anyone wants to share their
knowledge/experiences off this list, I'd be happy to hear from them.
--
Peter Baxendale
Durham University
School of Engineering
I think the fix should be simple,
> possibly just figuring out what compiler options to use.
>
I'd be happy to help. Last time I tried a mingw build of geda and pcb I
had very limited success
.
--
Peter Baxendale <[EMAIL PROTECTED]>
_
X283784D02*
X281763Y120709D01*
M02*
--
Peter Baxendale <[EMAIL PROTECTED]>
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-0500, Craig Niederberger wrote:
> You might want to consider building & installing gschem from the cvs
> repo. I found the performance significantly improved in FC6 compared
> to the latest rpm snapshot.
> Craig
>
--
Peter Bax
t having geda in a different place is a really good
> one--does anyone know where the FC6 repo defaults to putting geda? I
> had thought /opt/geda *was* a different place :) but probing around my
> system now, I realize I may be wrong!
--
Peter
les and petrol in litres. Meanwhile the kids only learn metric in
school (which gives us oldies a small advantage).
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Peter Baxendale <[EMAIL PROTECTED]>
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for footprints used by multiple projects, but
> how do I tell pcb and gsch2pcb to look there? Is there some
> configuration file for this? The pcb documentation mentions nothing
> about configuration files. Maybe pcb doesn't have one? Is the command
> line option to gsch2pcb th
to be programming pals these days,
> > and using FPGAs instead.
>
>I know of a few people using PALs, and I use them myself. I use
> PALASM under DOS on an x86 emulator. It works fine.
>
>-Dave
--
Peter Baxendale <[EMAIL PROTECTED]>
__
> Seriously though, I have absolutely no need for an office suite.
> Writing papers: 99% of the time I write them in plain text files in vi.
What a wimp. What's wrong with ed?
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ake immediate use of the reference design. Indeed, it
> would speed up the design process if I could just open a vendor's
> reference design & copy/paste the parts I wanted directly into my
> schematic instead of having to re-draw everything. Now that's design
> re-use!
I sw
nds more feasible. With the help of a
suitable config file you could guide it which layers to map to which
files, and maybe even assign pseudo pin connections to the points that
need to connect to other circuitry.
--
Peter Baxendale <[EMAIL PROTECTED]>
ommon to get reference designs that include gerbers, I
was wondering if it would be feasible to to convert these back into,
effectively, a pcb footprint. I'd have thought there was enough
information in the gerber and drill files to do this - but I admit I
haven't thought it through.
--
P
>
> Depends on how new your version of PCB is. Peter's suggestion is
> appropriate for recent releases since this feature was added not too
> long ago. I'm running 20060822. If Dave is using an older
> version, then my suggestion is appropriate.
>
> Joe T
>
>
Sorry. Hard to keep track of
Is there an easy command line way to generate an image (png or whatever)
from a gschem symbol file? I'd like to catalogue my symbols for other
users and a little picture would be nice.
Also, the same question for pcb footprints.
--
Peter Baxendale <[EMAIL P
On Tue, 2007-03-06 at 22:02 -0800, Dave N6NZ wrote:
> What is the easiest way to create "thermal vias"? Not a via with a
> thermal relief -- I can do that :) .. but a via with no thermal relief
> punched into polygons on both sides of the board that ends up getting
> filled with solder to help c
willingness to do it.
>
Quite right, but if they see the pain barrier as too high then they
won't do it, and I'd like them to do it, so I'd like to lower the
barrier a bit for them. Maybe if they see how good open source software
can be it might open their minds to other possibilit
> And i do a question, is gEDA an proper software to use during the
> formation academical process? I think yes that, this can be used for
> that.
>
> What do you think about?
A bit late to reply to this, but ...
We used gEDA in our Engineering course here at Durham University (UK)
School of En
I have to admit, this is one of the few aspects of Orcad I actually
liked better than pcb. When creating a copper fill you got (amongst
other things) a drop down list of nets, and you chose which one you
wanted the polygon connected to. This makes the connectivity dependent
on the net, rather than
> Yeah, great idea... is there any standard Perl Script under svn that most
> people use?
As well as Perl, there's a short Python program at
http://dlharmon.com/geda/footgen.html which I've found very useful. It's
easy to understand and customise even if you only have a little bit of
understandin
gt;
> /Jonatan
>
>
>
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>
--
Peter Baxendale
School of Engineering
Durham University
South Road
Durham
D
> problem 2:
> I get several errors like this:
>
> ERROR: Pin(s) with pintype 'unknown': U47:10 U48:10 U49:10 U50:10 U45:10
> [snip]
> are connected to pin(s) with pintype 'unknown': U47:10 U48:10
> U49:10 U50:10 U45:10
> [snip]
If you look in the gschem master attributes list it tells yo
I have a simple board which crashes pcb when I apply a thermal to a via.
Or, more specifically, when I apply and then remove the thermal. It's
100% reproducible, and other vias on the same board don't seem to have
the same problem. I can supply the pcb file and the trace output. I
checked out pcb f
We used to use DJGPP in our C programming classes. Now the students use
pcb in their ECAD classes. Wonder what he will turn his hand to next...
On Tue, 2006-11-07 at 18:11 -0500, Dave McGuire wrote:
> On Nov 7, 2006, at 6:05 PM, Paul Bunyk wrote:
> > Brings back fond memories of compiling my code
> >The parser starts at the end, moving towards the start of the string and
> >strips off lower case characters until it encounters any non-lowercase
> >character, then it stops. Thus Rp4 will be a valid element name. This
> >has been documented in the manual for at least 5 years now since I fir
> That's bizarre. Can anybody else reproduce this behavior?
> On my box, I select the component, pick Edit/Slot..., type in the
> new slot number (2 for a 7474-1), hit okay, and boom, I get the pins
> to change.
Weird. I just tried it again to make sure I wasn't going crazy. Here's
what
> However, if you change the slot number using either Edit/Slot...
> or by double clicking on the component and using the multiple attribute
> edit dialog box, then the slot number should update correctly.
None of these work for me. I'm not sure how to use the Edit/Slot...
function - it doe
I seem to be having slotting problems with gschem. If I add a 7474
component, for instance, and change its slot number to 2, the pin
numbers don't update. In the gschem log I see:
Opened file [/home/des0prb/geda/share/gEDA/sym/74/7474-1.sym]
numslots attribute missing
Slotting not allowed for this
> I am curious to know if your notes are available online, or are released
> under such a license that we can make them available to students here?
>
I've put them on my web page
( http://www.durham.ac.uk/peter.baxendale ). They are pdfs but I can
send you openoffice files if they are any use to
Thanks for the comment on refdes values. I'll add a few things to next
year's notes for the students.
It had never occurred to me to use anything but an upper case alpha
character followed by a numeric value for a refdes, but students have a
habit of trying the unexpected. It threw me for quite a
> Any lower case suffix is ignored. This is so you can, for example, place
> 4 discrete NAND gates on the schematic called U1a, U1b, U1c and U1d, and
> they will netlist into a single footprint / component, U1.
>
Ah, thanks - that explains exactly what I was seeing - CONNpower became
CONN.
> I'm
> A reason not to have long refdes values is clutter. Names that are seven and
> eight characters get difficult to place (legibly) on dense schematics and
> PCBs. A seven character refdes will probably take up more board area than most
> of you SMD components.
Yes, I agree entirely. What I meant w
Another dumb question. I teach a class of undergraduates about ECAD and
this year abandoned commercial tools in favour of geda. Students being
students, they tend to try things I wouldn't think of doing. Today, a
couple of them decided to be creative and on their schematic used names
like "CONNpowe
If you have a (component-library "...") line in your local gafrc file
(in $HOME/.gEDA), should that directory be searched before any others
for symbols?
I seem to find that if I save the design then reload it, gschem picks up
a symbol of the same name from the geda library instead of the one from
> Also the auto-router creates lines
> that have the join flag consistent with the setting for newly created lines
> (although the auto-router will never place a line within a polygon,
> people seem to want to add polygons to layers that the auto-router has used
> after it's done its routi
Ah, my mistake then. Maybe they were auto routed segments I'd ripped up
and manually routed. Apologies for the unwarranted slur on the auto
router.
> I don't believe these small segments are due to the autoroute process.
> I see them a lot and I've never used the auto-router. I believe they
>
> 3. Sometimes when DRC reports "copper areas too close", I go to the
> coordinates specified in the message and I cannot for the life of me
> find anything closer than 10 mils. (And I still have it checking for 5
> mil spacings.) Does DRC sometimes get fooled into thinking that
> connected lines s
> This brings up the question: how reliable is the auto-router anyway? Is
> it a reasonable idea to use it for non-critical projects - providing, of
> course, a person does a careful visual inspection of the traces?
I haven't seen an auto-router yet where you don't have to carefully
visually ins
I've noticed that if you mention the auto-router there's a deathly
silence here. Anyway, here goes...
I've noticed the following, which potential users of the auto-router
might like to be aware of:
1. The copper to copper clearance you get is half that specified in the
clearance parameter for the
Now I'm confused. I've ended up with some of the tracks showing a
polygon clearance of 10 mil (in an object report) whilst others show 5
mil. After a little experimentation it seems that if I draw a track
manually using the "signal" style (with "clearance" set to 10 mil and
line width set to 10 mil
Having tracked a board, I see that tracks generated using "signal" route
style have a clearance in polygons of 5 mil whilst those with "power"
style have 10 mil.
Where is this default clearance set? Under Route Style there's just a
clearance, set at 10 mil. Couldn't see any reference to polygon
cl
Hi Vaughn,
I didn't think you had to do anything special. When I have multiple
sheets I just use the same net name for signals that are the same (ie
connected together). gnetlist sorts it out when you give it multiple
pages.
Peter.
On Wed, 2006-09-27 at 06:36 -0700, Vaughn Treude wrote:
> Hello
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