On Thu, Sep 15, 2011 at 3:43 PM, DJ Delorie wrote:
>
>> But then I realized that I don't really understand what "all
>> connected objects" is supposed ot mean.
>
> Read as "all found objects" and it makes more sense.
>
Still not making sense to me, found by what metric?
On Thu, Sep 15, 2011 at 7:41 AM, Kai-Martin Knaak
wrote:
> Is there any way in PCB to select all unconnected track segments in a
> layout? This would come handy on redesign.
>
I thought "select all visible objects" followed by "unselect all
connected objects" might work. But then I realized that
On Mon, Sep 12, 2011 at 2:39 PM, John Doty wrote:
>
> On Sep 12, 2011, at 3:09 PM, Hannu Vuolasaho wrote:
>
>> I have been playing with one guitar amplifier project for a while and so far
>> the amplifier design has been more or less copy and paste and simulate and
>> guess from graphs. However
On Mon, Sep 12, 2011 at 2:09 PM, Hannu Vuolasaho wrote:
>
> Hi!
>
> I have been playing with one guitar amplifier project for a while and so far
> the amplifier design has been more or less copy and paste and simulate and
> guess from graphs. However I bumped in net this blog post
>
> http://nor
>> That's a good point. Where could things be best shared
>> between KiCad and gEDA?
>>
>
> Footprint editor ?
>
> https://github.com/bert/fped
>
> Fped lives in Ubuntu and Fedora, and maybe other distros, with support for
> KiCAD users.
>
> Anyone interested in a parametric footprint editor with
On Mon, Sep 5, 2011 at 9:53 PM, Bert Timmerman wrote:
> Hi Russell,
>
>> -Original Message-
>> From: geda-user-boun...@moria.seul.org
>> [mailto:geda-user-boun...@moria.seul.org] On Behalf Of Russell Dill
>> Sent: Monday, September 05, 2011 10:21 PM
>&
>> with one checked-out version you know
>> works, or maintain your own bugfix branch. Git head is where
>> development happens, and when we're bringing in big changes, stuff
>> breaks.
>
> This is why other projects like KiCAD provide a dedicated testing repo.
> Debian even has four stages (exper
On Fri, Sep 2, 2011 at 12:04 PM, Peter Clifton wrote:
> On Thu, 2011-09-01 at 20:26 -0700, Russell Dill wrote:
>> >> Throwing out a crazy idea.. in word-processors etc.., "styles" are found
>> >> in a drop-down combo-box. I know that doesn't fit so w
>
> Since we have such a good, algorithmic method for finding these shorts,
> perhaps we can write some code to do it for our puny human minds? ;)
>
> Usually, when I have power and ground shorted, it's because of a via placed
> some where that was accidentally assigned thermals to the wrong layer
>> Throwing out a crazy idea.. in word-processors etc.., "styles" are found
>> in a drop-down combo-box. I know that doesn't fit so well with where we
>> have space for the route-style selector, but just a crazy though.
>>
>
> One day, when we support an unlimited number of route styles. ;)
>
Yes,
On Thu, Sep 1, 2011 at 10:55 AM, Andrew Poelstra wrote:
>
> Hey all,
>
> Can we use toggle buttons instead of radio buttons for the
> route style selector? It would look like so:
>
> http://wpsoftware.net/andrew/dump/toggle.png
>
> This gives more clickable area and a cleaner look, I think.
>
Dun
On Wed, Aug 31, 2011 at 1:37 PM, Kai-Martin Knaak wrote:
> Russell Dill wrote:
>
>> I imagine I'm not the only one running a git mirror of
>> gedasymbols.org. If you rely on gedasymbols.org in any way, It'd be
>> wise to do the same.
>
> Is there a way to
On Mon, Aug 29, 2011 at 4:58 PM, Kai-Martin Knaak wrote:
> Peter Clifton wrote:
>
>> Yes - I got a message from DJ saying it has knocked his power and
>> internet down. (The server lives in DJ's basement).
>>
> Time for a mirror server on a different continent?
>
> I got used to rely on the presen
> One of my "dream projects" is to do a GUI for pcb that uses two or
> more monitors, with one monitor heavy on the toolbars and showing an
> overview "thumber" window, and the other monitor being 100% layout.
eh, one of the reasons I really like having two monitors is so I can
have reference info
On Mon, Aug 15, 2011 at 6:34 PM, Andrew Poelstra wrote:
>
> Exciting news everyone!
>
> I have just pushed the nanometer conversion patches to git HEAD.
>
>
> Please test and let me know how things are working. I have
> compiled all 56 commits (by script) to confirm that they can
> compile so "git
On Sun, Aug 7, 2011 at 7:47 PM, Rob Spanton wrote:
> Hey all,
>
> I've recently been playing around with designing footprints by
> describing a set of constraints that position features relative to each
> other. This is rather than specifying the absolute co-ordinates of
> every feature.
>
> I've
d how big of a reel do you have to send
> them? And you just cut tape the amount of parts you need to assemble
> the amount of boards you want to manufacture?
>
> On Wed, Jul 27, 2011 at 11:23 AM, Russell Dill wrote:
>> I'm planning on having some proto boards assembled
I'm planning on having some proto boards assembled by Advanced
Circuits (4pcb.com). And yes, I have to supply all the components, and
no, they don't provide storage until you've actually put the order in
(Many components are very moisture sensitive).
On Wed, Jul 27, 2011 at 10:28 AM, yamazakir2 w
82721122dae63a96c89d273bba7abd8b3e6e8337
#0 0x755db386 in _IO_vfprintf_internal (s=,
format=, ap=) at vfprintf.c:1620
#1 0x75691e38 in __vasprintf_chk (result_ptr=0x7fffc328, flags=1,
format=0xf3b170 "%s", args=0x7fffc348) at vasprintf_chk.c:68
#2 0x7728
I was selecting a net when PCB crashed.
82721122dae63a96c89d273bba7abd8b3e6e8337
*** glibc detected *** /home/russ/src/pcb/_install/usr/bin/pcb:
free(): invalid next size (fast): 0x027f4d60 ***
=== Backtrace: =
/lib/x86_64-linux-gnu/libc.so.6(+0x78a8f)[0x7f8d5f0a8a8f]
/lib/x86
On Tue, Jun 21, 2011 at 5:06 PM, DJ Delorie wrote:
>
> We use cmils for gerber (0.01 mil). PCB's DRC precision should be
> 0.000254 mm
Are you saying that 0.000254 mm should be added to your DRC rule if
exporting to gerber? (ie, a 4mil DRC would become 4.01mil)
On Tue, Jun 21, 2011 at 1:50 PM, Andrew Poelstra wrote:
> On Tue, Jun 21, 2011 at 01:29:02PM -0700, Russell Dill wrote:
>>
>> I've always worried about this too, especially when doing a design in
>> metric and sending it to an imperial board house. My guess is you need
On Tue, Jun 21, 2011 at 11:23 AM, Phil Taylor wrote:
> On 6/21/2011 6:53 AM, Richard Rasker wrote:
>>
>> So I wonder what tolerance PCB's DRC has? I realize that 0.006 mm (6
>> micron) is a tiny distance, but it can make all the difference between
>> an accepted and rejected board -- and thus dela
On Tue, May 31, 2011 at 2:09 PM, Levente Kovacs wrote:
> On Tue, 31 May 2011 21:59:04 +0100
> Thomas Oldbury wrote:
>
>> Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like
>> each jumper to have a refdes and BOM entry if possible.)
>
> What I'd do is define a copper layer. Draw
> To my knowledge this is not the case right now. Of course the pin numbers
> should not be shown on the schematics: they would use up too much schematics
> real estate and are not interesting anyway (even relatively simple and cheap
> FPGA devices like XC3S700A has 88 power pins in the 256 pins BG
As edge rates increase, signal intergrity (SI) becomes more and more
important, even for the hobbyist. Unfortunately, the models provided
by semiconductor vendors typically come in only 2 forms, encrypted
HSPICE and IBIS. No open tools exist for handling either. An open
HSPICE decryption utility wo
On Mon, May 30, 2011 at 10:15 AM, DJ Delorie wrote:
>
> Is there a quick way to check to see if a local repo is out of date
> relative to a remote repo? I'd like to write a shell script that
> rebuilds pcb but only if something's been committed to the master
> repo. Rather than check out the who
On Wed, May 25, 2011 at 2:40 PM, Colin D Bennett wrote:
> On Wed, 25 May 2011 23:03:06 +0200
> Gabriel Paubert wrote:
>
>> This said, most capacitors look to have a square profile, but
>> resonance frequencies observed on microstrip line change between
>> mounting the layers parallel or perpendic
On Wed, May 25, 2011 at 7:56 AM, Gabriel Paubert wrote:
> On Wed, May 25, 2011 at 07:11:49AM -0700, Colin D Bennett wrote:
>> On Wed, 25 May 2011 06:41:26 -0700
>> Colin D Bennett wrote:
>>
>> > (1) Why is RESC0603L/N/M much smaller than '0603'?
>> > (2) Why is there no similarly named set of RES
On Thu, May 19, 2011 at 10:27 AM, Stephan Boettcher
wrote:
> Kai-Martin Knaak writes:
>
>> Stephan Boettcher wrote:
>>
>>> The way to promote gedasymbols and to fix the default library is to
>>> remove the default library, except for a small set of very generic
>>> symbols.
>>
>> ack.
>> This set
I'm currently working on simulating IBIS models in ngspice. Its a work
in progress, but I have something that is at least somewhat usable at
this point. I put my current work on gEDA symbols:
http://www.gedasymbols.org/user/russell_dill/
I'll be doing more testing and refinement, and most importa
On Fri, May 13, 2011 at 9:34 AM, Colin D Bennett wrote:
>
> On Fri, 13 May 2011 12:14:45 -0400
> DJ Delorie wrote:
>
> >
> > IIRC my primary objection to the patch-as-was was, "where do we store
> > the TTF files?" PCB has no way to store binary blobs with the board,
> > and if you don't keep th
Did the clone succeed? Did you cd into the cloned repo?
On Wed, May 11, 2011 at 12:53 PM, Thomas Oldbury
<[1]toldb...@gmail.com> wrote:
� I'm getting this problem when trying to run the last command:
� thomas@thinkpadone:~/pcb2$ git checkout -b pcb+gl_experimental
� ori
On Wed, May 11, 2011 at 11:19 AM, Peter Clifton <[1]pc...@cam.ac.uk>
wrote:
On Wed, 2011-05-11 at 19:05 +0100, Thomas Oldbury wrote:
> Sometimes, I want to add an inner polygon area to a plane in PCB. The
> � � area might be a power supply which only has to cover a small
area; e
On Sun, May 1, 2011 at 3:49 PM, Rob Butts wrote:
> I'm using out and in symbols in gschem to label nets in a schematic and
> tie nets together without traces running everywhere. I set the net
> attribute of the corresponding out and in symbols in the schematic to
> the same value (clk for
On Wed, Apr 13, 2011 at 1:31 AM, Andy Fierman
wrote:
> If you are going to model the PA - particularly to look at resonance
> effects - then you should include reasonably accurate models for the
> inductors and capacitors which include their major parasitic
> components.
>
> The Murata Chip S-Para
On Mon, Apr 11, 2011 at 6:45 PM, John Doty wrote:
>
> On Apr 11, 2011, at 4:25 PM, Peter Clifton wrote:
>
>> I would advise a note of caution. In general, I don't like it when tools
>> start special casing things like this.. it just feels wrong.
>
> I've long thought it a minor design flaw that in
On Fri, Apr 8, 2011 at 2:18 PM, DJ Delorie wrote:
>
>> # shorting trace
>> Pad [ -1.550mm 0.000mm 1.550mm 0.000mm 0.5mm 0.5mm 0.700mm "c" "c"
>> "square" ]
>
>
> Perhaps a new flag for pads that means "non-net copper" ? Then
> "square,nonnet" (for example) tells 'o' to ignore that copp
On Fri, Apr 8, 2011 at 9:39 AM, rickman wrote:
> On 4/7/2011 1:13 PM, Stephan Boettcher wrote:
>>
>> rickman writes:
>>
>>> I have to say I am philosophically opposed to any feature that allows
>>> a design to pass DRC when the layout differs from the schematic.
>>
>> Just to get the terminology
2011/4/7 Rubén Gómez Antolí :
> Hi:
>
> El 06/04/11 16:42, John Doty escribió:
>>
>> On Apr 6, 2011, at 8:26 AM, Dave McGuire wrote:
>>
>>> On 4/6/11 3:01 AM, Stephan Boettcher wrote:
>
> Specifically, the suite misses a way for fast turnaround of schematic
> modification, simulation an
On Wed, Apr 6, 2011 at 2:51 PM, Stephen Ecob
wrote:
>> What, if there was a way to flag a track as "don't look" for connectivity
>> check? You'd attach the flag to the segment that bridges the domains.
>> That way, the DRC check would still be sensitive to violations at other
>> places. Such a DRC
On Wed, Apr 6, 2011 at 2:41 PM, Kai-Martin Knaak wrote:
> Kovacs Levente wrote:
>
>> I think the workaround in gEDA is still a good way to go.
>
> The bogus DRC error potentially masks erroneous connections between
> the planes elsewhere.
>
> What, if there was a way to flag a track as "don't loo
On Tue, Apr 5, 2011 at 1:53 AM, Kovacs Levente wrote:
> On Mon, 4 Apr 2011 23:30:21 -0700
> Russell Dill wrote:
>
>> The common way to track common ground planes seems to be to place a
>> jumper between the planes so that the netlist can be sane. This
>> requires a co
The common way to track common ground planes seems to be to place a
jumper between the planes so that the netlist can be sane. This
requires a component to be placed on one of the outer layers of the
board, which is a bit of an annoyance. Is there any other way of doing
this? Maybe some kind of hac
On Fri, Apr 1, 2011 at 2:19 PM, Joshua wrote:
> Hey guys. I wrote a tool which exports and imports the properties from a
> project to and to a csv file. The format is simular to that of the bom2
> format as it groups lines together which have similar data. This way I
> could use oocalc to mass
On Fri, Feb 25, 2011 at 4:20 PM, Cyril Hrubis wrote:
> Hi!
>> Tastes may vary, but some years ago when I went looking for a clean
>> C++ matrix math class library, I was favorably impressed by newmat
>> http://www.robertnz.net/nm_intro.htm
>> Operator overloading with a clear purpose!
>
> Thanks
On Mon, Feb 21, 2011 at 12:40 AM, Stephan Boettcher
wrote:
> Russell Dill writes:
>
>> On Sun, Feb 20, 2011 at 10:05 AM, Kai-Martin Knaak wrote:
>>> Russell Dill wrote:
>>>
>>>> I'm just wondering what everyones preferred method of breaking up
&g
On Thu, Feb 24, 2011 at 3:04 PM, Martin Kupec wrote:
> Hi,
>
> I have written something to: http://geda.seul.org/wiki/geda:pcb_layers
>
> It is still a bit work in progess, but you can start editing it to fit your
> ideas. I have tried to incorporate all ideas discussed.
>
> Martin Kupec
>
On Thu, Feb 24, 2011 at 8:50 AM, Peter Clifton wrote:
> On Thu, 2011-02-24 at 08:38 -0700, John Doty wrote:
>> On Feb 24, 2011, at 8:22 AM, Peter Clifton wrote:
>>
>> > Means C didn't find the function, and it assumes it returns integer in
>> > that case. Dumb convention IMO.
>>
>> "C is quirky, f
I'm starting a new design and all my components are metric based,
including a few 1mm pitch BGA components. I'd really like to do the
layout in metric, but I'm worried about two factors. The first of
which is that PCB does not yet have the option to store things
internally in metric (at least from
On Sun, Feb 20, 2011 at 10:05 AM, Kai-Martin Knaak wrote:
> Russell Dill wrote:
>
>> I'm just wondering what everyones preferred method of breaking up
>> power/ground planes is.
>
> My preferred method is to break the planes as little as possible :-)
> IMHO, a con
I'm just wondering what everyones preferred method of breaking up
power/ground planes is. Way back when I used to break them up by using
the polygon editor which was really a pain. It seems like using a 0
width trace might work well, but it produces a zero width line on the
gerber, bummer.
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