Hi Vinny,
Once you have edited and saved a part, go back to the schematic, select
the part, then select "Edit" and then "Update Component" or use the
shortcut "ep." This should reload that component and update the schematic.
If you have multiple instances of the component, highlight them all
Hi Peter, thanks for your reply.
I am sure that a lot of users have learned the way it acts and have gotten
used to it. Changing would be a bother. I just want to customize it to my
liking. I don't like having to left click and then also right click to end
my net. I just want to right click
As a new gEDA used who has completed a couple schematics now, I have a few
comments and questions. There are various inconsistencies in what the
mouse buttons do between various functions. Some of these are annoying and
could be modified to make it all easier to use. For example:
When you ar
I think grefdes is what I remembered reading about. I have now tried it
and in general, it does a nice job. Now I need to learn some Perl to
understand it better. It does not seem to understand about schematic
hierarchy however. It renames/renumbers even refdes names for the
hierarchy input
Hi Dan,
Yes, that seems to have fixed the problem. My layout guy was able to
directly read in the netlist to PADS without any difficulty.
Thanks,
Steve
On Mon, 25 Feb 2008 15:43:42 -0800, Dan McMahill <[EMAIL PROTECTED]> wrote:
> could you verify that the attached patch works correctly?
>
>
Yes, exactly. I thought I had seen something about someone else having
done this before. There was something about changing the refdes from the
composite sheet/part style into a flat numbering system. Maybe I'm just
dreaming. Anyway, I'll take a look at grefdes tomorrow and see what I can
m
I believe the answer to both these questions is yes.
Steve
On Mon, 25 Feb 2008 12:31:49 -0800, Stuart Brorson <[EMAIL PROTECTED]> wrote:
>> If Pads expects CR-NL should the netlist generator output CR-NL?
>
> Interesting question. Is it safe to assume that PADS runs exclusively
> on Windoze?
>
Yes, I ran the file through unix2dos and that fixed the problem. Thanks to
Dan McMahill and others who gave suggestions for this problem.
Steve
On Mon, 25 Feb 2008 11:27:01 -0800, Stuart Brorson <[EMAIL PROTECTED]> wrote:
> You can always try running unix2dos on the file before shipping it to
I have designed a circuit and created a pads netlist to send to the person
who is doing my layout. He said that PADS will not accept the netlist file
directly. He can get around the problem by first opening the file with
Excel and then re-saving it. Then PADS will read it just fine. I will tr
When creating a hierarchy you end up with refdes numbers with the top
level refdes of the circuit symbol, a slash, and then the underlying
refdes such as X101/R102. I would like to end up with refdes on the top
level of R1, R2, etc. and parts from the underlying schematic be R101,
R102, etc
e is promoted, that I'll have
to leave to another day. It is now working well enough for me to complete
this project.
Thanks to all who helped,
Steve
On Mon, 11 Feb 2008 14:55:51 -0800, John Griessen <[EMAIL PROTECTED]>
wrote:
> Steven Taylor wrote:
>> My symbol, that I c
Yes, John, that would be helpful. It would give me a second sample to try
here and see where I may be going wrong.
Thanks,
Steve
>
> Want me to create a schematic set with embedded symbols and send it to
> you for another example to follow?
> The schematic is for some free-published hardware..
My symbol, that I created, that represents my lower level schematic has
pins with only pin numbers, pinseq numbers, and pin labels. The pin labels
match the refdes on the IO connectors on the underlying schematic. That is
the way it was done on the gTAG example. I tried assigning pintypes to
those particular nets were being flaged is that they were the only
nets that had only one pin connection on the lower level schematic. There
must be a setting somewhere to stop this behavior. I just have no idea
where it would be.
Steve
On Mon, 11 Feb 2008 13:47:54 -0800, Steven Taylor
Actually, I have to take that back, the nets do show up correctly
connected for all of the IOs, but the pins on the lower level schematic
also show up in the net list as nets with only a single pin. So those nets
in question are actually in the net list twice, once as single pin nets
and th
The net list comes out OK except for two of the nets which don't connect
through between the upper level and the lower level schematics.
Steve
On Mon, 11 Feb 2008 13:09:40 -0800, Peter Clifton <[EMAIL PROTECTED]> wrote:
>
> On Mon, 2008-02-11 at 13:07 -0800, Steve Taylor wrote:
>
>> I am evide
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