I haven't tracked VBPP recently, but as for VBS, may I ask *why* do you
want it?
Icarus Verilog is way more advanced and actively developed.
VBS was developed more than 10 years ago (before Icarus), but it was
Jimen Ching's University graduation project and AFAIK it wasn't
maintai
If you are looking at commercial tools as well, you can take a look at:
http://www.tarayinc.com/overview.php
Udi
On Sun, Sep 28, 2008 at 8:44 AM, Ben Jackson <[EMAIL PROTECTED]> wrote:
> Projects with microcontrollers and FPGAs often have a lot of flexibility
> in how things get connected. My
On Feb 10, 2008 1:11 AM, DJ Delorie <[EMAIL PROTECTED]> wrote:
> > Also note the use of blocking assignments (=), not non-blocking
> > assignments (<=). It is recommended to use blocking assignments for
> > combinatorial blocks and non-blocking assignments for sequential
> > (clocked) blocks.
>
>
On Feb 9, 2008 3:14 AM, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
>
> > Was the need for the 2$ part due to pins or due to resources?
>
> Resources. There weren't enough intermediate nodes to do all the
> logic equations, I ran out of "product terms". The minimal design in
> a '72 used about 60% o
VCD stands for "Value Change Dump"
http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Verilog/LRM/HTML/15/ch15.2.htm
Udi
On 7/2/07, Werner Hoch <[EMAIL PROTECTED]> wrote:
Hi Karl and all,
On Thursday 28 June 2007 22:12, Karl. wrote:
> On Thu, Jun 28, 2007 at 07:59:19PM +0200, Werner Hoch wrote:
On 4/5/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
I've made a BMP image format creating module for fun.
Looks like it's not so fun after all :-(
I maintain a 640x480 24-bits per pixel buffer and then write the data
out to a file.
At first I used a reg array, but came to find that eac
6 matches
Mail list logo
