I am off for a few months. I don't want email piling up.
unsubscribe geda-user@seul.org
unsubscribe: unknown list 'geda-user@seul.org'.
Help for [EMAIL PROTECTED]:
unsubscribe geda-user
unsubscribe: unknown list 'geda-user'.
Help for [EMAIL PROTECTED]:
Both refus
I have not been involved with PAL/PLD's for 10 years. Then, we used
ABEL, etc., in the programming process.
Is it possible to synthesize logic for PAL/PLD devices with gnetlist
and iverilog?
I am particularly interested in the 16V8.
I use FreeBSD, and, have the ports tree.
tomdean
___
How about 4 diodes and current limiting resistors?
tomdean
v 20060123 1
C 11100 37100 1 0 0 ATtiny28_DIP.sym
{
T 13500 43000 5 10 1 1 0 6 1
refdes=U?
}
C 15700 40500 1 0 0 diode-1.sym
{
T 16000 41000 5 10 1 1 0 0 1
refdes=D?
}
C 14600 40600 1 0 0 resistor-1.sym
{
T 14800 40900 5 10 1 1 0 0 1
refd
The spice3f5 help panel on lossy transmission lines states:
3.3.3. Lossy Transmission Line Model (LTRA)
The uniform RLC/RC/LC/RG transmission line model (re-
ferred to as the LTRA model henceforth) models a uniform
constant-parameter distributed transmission line. The RC
and
Thanks for the replies.
I have not looked into this type analysis for some 20 years. I still
have my Terman reference!
The value/unit is specified in the Spice 3f5 help pages.
I used the value/foot specifications for Belden 9914 Coax and
specified the length in feet. I added the center conduct
I suspected I did not need two lines to model a normal coax at
reasonable frequencies. Thank you.
Why are my results very different than I see in practice?
Is there a better model?
tomdean
___
geda-user mailing list
geda-user@moria.seul.org
http://w
I am using Spice 3f5, attempting to model a coax line. I am a nubie
at this. The lossless example uses two lines to model one coax. Do I
need to do this with the ltra model? It does not seem to make a
difference.
I get funny results. I use
ac dec 100 1 1000meg
plot db(v(4)/v(2))
I see what
That was it. source-library.
Thanks.
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
I put gafrc in $HOME/.gEDA
tomdean
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
I am having problems with hiearchy.
I want to have a hiearchy with an inout bus and a couple in and out
pins. So, I created a symbol and associated schematic, counter below.
The symbol has pins, and a source attribute.
I have (component-library "./") in my ~/.gEDA/gafrc.
I created a schematic,
I know little about jfet's. So, I started playing with a model I took
from onsemi. The only parameter I can match to the datasheet is VTO.
I tried dc v2 -1 1 .1 and looked at v1#branch and v2#branch. Not what
I expected.
So, I think I am doing something wrong.
tomdean
.MODEL 2n5486 njf (
More random segment faults. Gdb points to autosave().
This seems to happen more often when I have
(component-library "/usr/home/tomdean/cad/sym")
in ~/.geda/gafrc
Any ideas?
tomdean
___
geda-user mailing list
geda-user@moria.seul.org
http://www.se
I have a lf353 model, below, included in a .sch, also below.
I use gnetlist -g spice.sdb xxx.sch.
I get an output that looks OK.
Op and dc produce what I expect. However, ac and tran do not.
dc v101 -1 +1 .001
plot vout
shows linear ramp, gain=10
ac dec 100 1 10meg
plot vout
shows horizona
I filled out the contribution page, but, have some questions.
I don't know what library this belongs in. It is a serial-in, 18-bit,
dual channel audio ADC.
Also, I have three pins,
15 VsL - A supply voltage that may be different than Vcc. I have
pintype pwr.
9 VsR - A supply vol
I have been seeing a random signal 11, Segmentation fault in gschem
for the past few days. I cannot pin it down to any action on my part.
Often it happens when gschem does not have focus. Other times it
happens when I am doing something with gschem, but, never the same
thing, as far as I can tell
Thanks, Dan.
I updated to 20060422. I can load the netlist.
tomdean
For FreeBSD,
--- Makefile~ Sun Jul 9 23:38:55 2006
+++ MakefileWed Jul 26 14:37:44 2006
@@ -6,7 +6,7 @@
#
PORTNAME= pcb
-PORTVERSION= 20060414
+PORTVERSION= 20060422
CATEGORIES=cad
MASTER_SITES= ${MAS
I applied the patch to src/file.c, rebuilt and reinstalled pcb.
No change!
Something is strange with my installation. I will rebuild everything
related to pcb.
===> pcb-20060414 depends on executable: gm4 - found
===> pcb-20060414 depends on executable: gmake - found
===> pcb-20060414 dep
I deleted the file, then did file->save layout.
>From the tutorial,
# pcb board.pcb
select->disperse all elements
drag U101 to a new location
file->save layout
file->quit program
OK to lose data? - seems to be a disconnect here
...
file->save layout as
xx.pcb
click open
I have some other strangeness. From the tutorial, one.sch, two.sch,
and project file.
# gsch2pcb project - seems OK.
# pcb board.pcb - loads all elements stacked in the upper left cornet
file->save layout - closes popup, but, does NOT write a file!
select->disperse all elements
file->quit p
I tried
file->load netlist file
highlight board.net
click open
The load popup closed, no messages, nothing.
window->message log
is empty
connects->optimize rats nest
log window pops up with
'Can't add rat lines because no netlist is loaded.'
file->load v
Anyone have an idea why I cannot reproduce the tutorial on my system?
tomdean
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
I cannot reproduce the tutorial pcb. Are the .pcb and .net files from
gsch2pcb available? If not, can someone post them?
tomdean
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
I zapped all that - actually copied all of usr/local/share/gEDA to
~/cad/gEDA and set the environment variables GEDADATA[RC] to point
there. Things worked.
I later zapped all that.
I created a gnetlistrc containing
(scheme-directory "/usr/home/tomdean/cad/verilog/work")
I copied gnetlist.scm
My goal is to do slot-level simulation, to use a gschem term.
I started with an existing schematic. After jumping thru several
hoops, I am still not there.
The library for common ttl components may be more difficult than it
first appears.
Maybe the better way to go is the verilog library... Ne
It looks like if I change all symbols to contain an attribute
VERILOG_PORTS=POSITIONAL
the pin number will be commented out.
I want to avoid having two symbols for everything.
I am looking into something to carry over positional from the top
level schematic.
tomdean
_
I want gnetlist to use a scheme file other than in
/usr/local/share/gEDA/scheme.
I installed a local copy of gnetlist.
./configure --prefix=/usr/home/tomdean/cad/gEDA \
--exec-prefix=/usr/home/tomdean/cad/gEDA
I have a local gafrc containing
(scheme-directory "/usr/home/tomdean/cad
How do I cause 'gnetlist -g verilog' to pick up the pinlabel rather
than the pin number for the module port name?
Is there a doc that describes the flow in gnetlist?
tomdean
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-b
That was it.
I renamed everything .v and now, it finds all the modules.
Thanks,
tomdean
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
I tried the -y switch.
I have a directory ../modules with files like ver_7400 containing
module ver_7400(O,A,B);
...
endmodule
My source file contains ver_7400 U8 (...)
iverilog -y ../modules source.vl
complains
source.vl:54: error: Unknown module type: ver_7400
...
I tried
iveril
I tried the tutorial - same result.
Here is the pcb file.
tomdean
=
# release: pcb 1.6.3
PCB("" 6000 5000)
Grid(10 0 0)
Cursor(10 270 3)
Flags(0x00d0)
Groups("1,2,3,s:4,5,6,c:7:8:")
Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,
Pcb displays no messages on the terminal.
I started fresh. Same result. The result of the commands attached,
as well as some version information, .sch, .net.
tomdean
=== gschem ===
# gschem mytest.sch&
[3] 50267
gEDA/gschem version 20
No, I did not get a little window with the netlist. When I selected
the .net file from the pop-up and clicked open, the window closed.
Nothing appeared in the log window.
windopw->netlist does not appear to do anything.
tomdean
___
geda-user mailing
I am a newbie w/ PCB.
I created a schematic with gschem. Gnetlist -g drc2 reports a couple
mis-matched pins, passive connected to input, etc. Gnetlist -g geda
produces a correct looking listing.
gsch2pcb reports no errors. The resulting .net looks OK.
Pcb only complained of no font informatio
Is this off topic?
How do I cause iverilog to pick up modules from files?
I tried '-I../modules'
I created a schematic with device equal to the verilog file containing the
module definition. For example,
in gschem,
device ver_7474
in the file,
../modules/ver_7474
module ver_747
How do I generate verilog with gnetlist? I have a simple schematic
with a 7400 and a 7474, below.
I used gnetlist -g verilog -o test.vl test.sch. Gnetlist complains of
pin numbers not being valid identifiers.
I made symbols with pintype CHIPIN, CHIPOUT, etc., naming these
7400-vl.sym and 7474-v
> Sounds like the infamous slice bug. Try:
> export G_SLICE=always-malloc
Thanks, that seemed to fix the problem.
tomdean
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
I had a core dump on exit from gEDA 20050313, installed from the
FreeBSD potrs tree.
I changed the Makefiles to use gEDA 20060123, including libgeda.so.25.
Building and installing gEDA 20060123 reported no errors.
Starting gschem seems OK. On exit, I get
Segmentation fault (core dumped)
Thanks for the reply,
I went back to the FreeBSD port, 20050313. With that, I get a core
dump on exit, and sometimes a dump with I hit delete!
Looking at some other things, I have some funny things happening.
Like, the copy buffer in X. If I highlight text in one window and try
to paste it into
38 matches
Mail list logo
