Re: RE: gEDA-user: Need a Verilog test run

If it can wait until monday, I'll run it using Aldec.- Original Message -From: "Schulmeyer, K" Date: Saturday, January 20, 2007 6:08 pmSubject: RE: gEDA-user: Need a Verilog test runTo: gEDA user mailing list > Here is the partial output from Cadence Verilog-XL> > Compiling source file "

RE: gEDA-user: Need a Verilog test run

Here is the partial output from Cadence Verilog-XL Compiling source file "test_case.v" Highest level modules: test At 1 value is 00 At 2 value is 0x At 3 value is 11 At 4 value is 0x At 5 value is 00 At 6 value is 00 L13 "test_case.v": $finish at si