> I might have put the attribute string "PCB::non-copper" in a #define
> somewhere, but if the string is canonical, I guess it doesn't hurt to
> place it explicitly in the code.
Perhaps we should tell DRC about all sorts of attributes? Then we can
do layer-specific ones. I'd want to use DRC::*
On Tue, 2010-09-07 at 06:56 +, Ineiev wrote:
> On 9/6/10, Peter Clifton wrote:
> ...
> > confusing "non-copper" with "skip-drc" is
> > probably a bad idea.
> ...
>
> Thank you, your suggestion is really reasonable.
>
> I renamed the attribute to PCB::non-copper
> and corrected the variable n
On 9/6/10, Peter Clifton wrote:
...
> confusing "non-copper" with "skip-drc" is
> probably a bad idea.
...
Thank you, your suggestion is really reasonable.
I renamed the attribute to PCB::non-copper
and corrected the variable name and comments accordingly;
probably it does not make the patch per
On Mon, 2010-09-06 at 15:32 +0200, Kai-Martin Knaak wrote:
> Peter Clifton wrote:
>
> >> Why don't we just push this patch to HEAD? This works just great.
> >
> > One minor nit..
> >
> That is, the patch is rejected because of this minor nit?
I don't accept / reject patches per-se.. I was just
On Mon, 2010-09-06 at 09:30 +0200, Kovacs Levente wrote:
> On Sun, 05 Sep 2010 22:19:08 +0100
> Peter Clifton wrote:
>
> > I'd keep the "non-copper" / "skip-drc" ideas separate. We might (at
> > some point) have DRC rules for non-copper layers (not that I can
> > think of them at the moment, perh
Peter Clifton wrote:
>> Why don't we just push this patch to HEAD? This works just great.
>
> One minor nit..
>
That is, the patch is rejected because of this minor nit?
---<)kaimartin(>---
--
Kai-Martin Knaak tel: +49-511-762-2895
Universität Hannover, Inst. f
On Sun, 05 Sep 2010 22:19:08 +0100
Peter Clifton wrote:
> I'd keep the "non-copper" / "skip-drc" ideas separate. We might (at
> some point) have DRC rules for non-copper layers (not that I can
> think of them at the moment, perhaps apart from silk layer(s)).
Component outline vs. keep-in compone
On Sun, Sep 5, 2010 at 2:19 PM, Peter Clifton <[1]pc...@cam.ac.uk>
wrote:
On Sun, 2010-09-05 at 00:18 +0200, Levente Kovacs wrote:
> On Sat, 4 Sep 2010 11:24:38 +
> Ineiev <[2]ine...@gmail.com> wrote:
>
> > Probably this patch may be used as a workaround.
>
Peter Clifton wrote:
> What is useful is that the "outline" / "route" titled layers don't
> get pads flashed on them when exporting gerbers. All other (copper)
> layers get the pads on them, which would be a problem for an
> outline plot.
Apparently not for my preferred fab. When asked, they tol
On Sat, 2010-09-04 at 22:56 +0200, Pawel Kusmierski wrote:
> On Sat, Sep 4, 2010 at 1:11 PM, Peter Clifton wrote:
> > As a kludge, call your layer by one of the magic names "outline" or
> > "route" and it will be ignored by the DRC, and treated as non-copper.
> >
>
> Peter, thanks for the tip.
>
On Sun, 2010-09-05 at 00:18 +0200, Levente Kovacs wrote:
> On Sat, 4 Sep 2010 11:24:38 +
> Ineiev wrote:
>
> > Probably this patch may be used as a workaround.
>
> Why don't we just push this patch to HEAD? This works just great.
One minor nit..
I'd keep the "non-copper" / "skip-drc" ideas
On Sun, Sep 5, 2010 at 6:42 AM, Ineiev wrote:
> On 9/4/10, DJ Delorie wrote:
>>> Ineiev, thanks for the patch, it applied fine. However, I'm unable to find
>>> the
>>> (Edit->Edit attributes of->Current Layer). Is it placed somewhere else,
>>> or can I manually edit the .pcb file for the same res
On 9/4/10, DJ Delorie wrote:
>
>> Ineiev, thanks for the patch, it applied fine. However, I'm unable to find
>> the
>> (Edit->Edit attributes of->Current Layer). Is it placed somewhere else,
>> or can I manually edit the .pcb file for the same result?
>> I'm using pcb source tree from git, version
> Ineiev, thanks for the patch, it applied fine. However, I'm unable to find the
> (Edit->Edit attributes of->Current Layer). Is it placed somewhere else,
> or can I manually edit the .pcb file for the same result?
> I'm using pcb source tree from git, version 1.99z.
Do you have a local ~/.pcb/gp
On Sat, 4 Sep 2010 11:24:38 +
Ineiev wrote:
> Probably this patch may be used as a workaround.
Why don't we just push this patch to HEAD? This works just great.
Thanks,
Levente
--
Levente Kovacs
http://levente.logonex.eu
___
geda-user mailin
On Sat, Sep 4, 2010 at 1:24 PM, Ineiev wrote:
> Probably this patch may be used as a workaround.
>
> Put your non-copper layer into a distinct layer group
> (File->Preferences->Layers, Groups Tab), add to the layer an attribute
> named "PCB::skip-drc" (Edit->Edit attributes of->Current Layer),
> a
On Sat, Sep 4, 2010 at 1:11 PM, Peter Clifton wrote:
> As a kludge, call your layer by one of the magic names "outline" or
> "route" and it will be ignored by the DRC, and treated as non-copper.
>
Peter, thanks for the tip.
I may be doing something wrong, but even following the tips at
http://www
On 9/3/10, Stefan Salewski wrote:
> On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote:
>>Can I get pcb to either treat a layer other than the default silk as
>>non-metal
>>(so it would not short pads and mess up nets),
> No, currently we have only one silk layer. You may "miss-
On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote:
As a kludge, call your layer by one of the magic names "outline" or
"route" and it will be ignored by the DRC, and treated as non-copper.
Regards,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of
On Fri, Sep 03, 2010 at 06:40:05PM +0200, Pawel Kusmierski wrote:
>
> Is anybody willing to elaborate on how difficult would it be
> to modify the pcb source code to color-differentiate three or four
> silk layers and be able to selectively hide/show them?
>
It will probably be more work than it
No, FreePCB is a separate project with no links in any way. I have
used it for a couple of projects and like it pretty well, but it is
hard to get changes made. The developer was on a hiatus for some
time, but is back now. He has a long list of bug fixes and
suggestions people would like to
On Fri, Sep 3, 2010 at 6:49 PM, Rick Collins wrote:
> I can't answer your question, but I have one of my own. I use FreePCB and
> have requested, along with others, that we be able to designate layers as
> "documentation" such as assembly info, mechanical details, etc. Is that
> what you are loo
I can't answer your question, but I have one of my own. I use
FreePCB and have requested, along with others, that we be able to
designate layers as "documentation" such as assembly info, mechanical
details, etc. Is that what you are looking for or do you want these
layers to be usable to prod
On Fri, Sep 3, 2010 at 1:51 PM, Stefan Salewski wrote:
> On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote:
> > Dear fellow GEDA-users,
> > Can I get pcb to either treat a layer other than the default silk as
> > non-metal
> > (so it would not short pads and mess up nets),
> Pleas
On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote:
> Dear fellow GEDA-users,
>Can I get pcb to either treat a layer other than the default silk as
>non-metal
>(so it would not short pads and mess up nets),
Please note, your SUBJECT may be misleading...
No, currently we have on
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