On Sunday 18 February 2007 16:44, Dave McGuire wrote:
> I really like this idea as an architectural concept.
The architectural concept is there now. The December 2006
snapshot supports plug-ins. The one that is coming extends it.
What I am not sure about is how much to link in to the main
On Sunday 18 February 2007 20:01, Magnus Danielson wrote:
> I on the other hand would have preferred VHDL. There is many
> reasons for it.
In the long run it really doesn't matter. The simulator core
handles lists of blocks with connections. Anything more than
that is handled through plug-ins.
From: John Griessen <[EMAIL PROTECTED]>
Subject: Re: gEDA-user: vhdl and gschem
Date: Sun, 18 Feb 2007 18:54:46 -0600
Message-ID: <[EMAIL PROTECTED]>
> al davis wrote:
> For manual entry, the
> > Verilog format is clear, compact, and regular. .. far superior
> >
al davis wrote:
For manual entry, the
Verilog format is clear, compact, and regular. .. far superior
to the Spice format. The next real release of gnucap will use
Verilog as the default netlist language, and read Spice files
through a plug-in.
Thanks for that decision Al,
I've always liked
On Feb 18, 2007, at 4:15 PM, al davis wrote:
Another comment on gnucap I am thinking of having the
simulator core include no models at all, not even a resistor.
All models are attached as plugins. There will be a
development snapshot in a day or so that makes serious use of
plugins, and p
On Friday 16 February 2007 17:48, Stuart Brorson wrote:
> That being said, I must say that using a schematic capture
> package to do Verilog or VHDL seems to defeat the purpose.
Actually, VHDL and Verilog are very good as netlist languages.
For automated generation, either is adequate, and VHDL
On Feb 16, 2007, at 6:49 PM, Ostheller, Joel A. wrote:
Yes. Pick yourself up a copy of Peter Ashenden's "The Designer's guide
to VHDL". Additionally you may want to get a copy of the IEEE VHDL
LRM.
There is no reason to use schematic capture packages to do Verilog or
VHDL. Some have claimed
From: "Ostheller, Joel A. " <[EMAIL PROTECTED]>
Subject: RE: gEDA-user: vhdl and gschem
Date: Fri, 16 Feb 2007 17:49:38 -0800
Message-ID: <[EMAIL PROTECTED]>
> Yes. Pick yourself up a copy of Peter Ashenden's "The Designer's guide
> to VHDL". Add
2:48 PM
> To: gEDA user mailing list
> Subject: Re: gEDA-user: vhdl and gschem
>
> I applaude your efforts to understand the VHDL back-end. It's too bad
> it doesn't seem to work easily; I do think that it should "just work".
>
> That being said, I must sa
From: "Chitlesh GOORAH" <[EMAIL PROTECTED]>
Subject: Re: gEDA-user: vhdl and gschem
Date: Fri, 16 Feb 2007 23:36:22 +0100
Message-ID: <[EMAIL PROTECTED]>
> Hello there,
> I successfully created a vhdl file from
> http://tux.u-strasbg.fr/~chit/cours_vhdl/halfadde
I applaude your efforts to understand the VHDL back-end. It's too bad
it doesn't seem to work easily; I do think that it should "just work".
That being said, I must say that using a schematic capture package to
do Verilog or VHDL seems to defeat the purpose. That is, these
text-based logic lang
Hello there,
I successfully created a vhdl file from
http://tux.u-strasbg.fr/~chit/cours_vhdl/halfadder.sch
http://tux.u-strasbg.fr/~chit/cours_vhdl/output.net.
However, since my schematic includes some and2 and or2, the output.net
includes the respective components, but if I compile the vhdl fil
On 2/11/07, Magnus Danielson wrote:
However, in general what you do want to do is to design in input and output
You want to go into the VHDL symbol table and use ipad-1, opad-1 and iopad-1
which will map over to VHDL in, out and inout declarations of Std_Logic type.
Assign the value of these to
From: "Chitlesh GOORAH" <[EMAIL PROTECTED]>
Subject: gEDA-user: vhdl and gschem
Date: Sun, 11 Feb 2007 20:03:47 +0100
Message-ID: <[EMAIL PROTECTED]>
Hi!
> Hello thre,
>
> I'm trying to make a VHDL file from a mere simple half adder schematic:
> http://tux.u-strasbg.fr/~chit/half_adder/adder.sch
El dom, 11-02-2007 a las 20:03 +0100, Chitlesh GOORAH escribió:
[snip]
> I'm trying to make a VHDL file from a mere simple half adder schematic:
> http://tux.u-strasbg.fr/~chit/half_adder/adder.sch
>
> with:
> gnetlist -g vhdl adder.sch -o output.vhdl
> http://tux.u-strasbg.fr/~chit/half_adder/out
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