Re: gEDA-user: [Icarus Verilog] How to synthesis a flip-flop with asynchronous reset

Hi, r, Thank you very much. You suggestion works fine. I am not quite familiar with Verilog grammar. Seems it is my fault missing the "posedge" for reset. :) Best regards, Yujie Wen r 写道: > On Wed, Mar 11, 2009 at 11:12 AM, 温宇杰 wrote: > >> always @(posedge CLK or RESET) begin >> if (RESET =

Re: gEDA-user: [Icarus Verilog] How to synthesis a flip-flop with asynchronous reset

On Wed, Mar 11, 2009 at 11:12 AM, 温宇杰 wrote: > > always @(posedge CLK or RESET) begin > if (RESET == 1) begin Q = 0; > end I don't know much about iverilog but you may want to try this form: always @(posedge CLK or posedge RESET) begin Regards, -r __

gEDA-user: [Icarus Verilog] How to synthesis a flip-flop with asynchronous reset

Hi, I am writing some netlist generator in the Icarus Verilog 0.8 release for our own FPGA-like devices. But I ran into a question that whether Icarus Verilog can synthesis out flip-flops with asynchronous reset input. When I run iverilog with command "iverilog -tfpga -parch=virtex test.v" and th