>
>The most likely reason is that the pins themselves are violating the
>spacing rule that you've allowed the autorouter.
>harry
>
Hello Harry,
this reminds me to ask one question. If I place some TQFP and route it
manually, then I run DRC, I get a plenty of errors. Is it possible
Hi,
First time using TSSOP48.
All rats, except those to/from TSSOP48, were successfully
autorouted.
Is this a limitation in version 20080202 of pcb, or am I missing
something?
Stan
The most likely reason is that the pins themselves are violating the
spacing
On Jul 14, 2007, at 5:08 PM, Ben Jackson wrote:
> On Sat, Jul 14, 2007 at 04:43:38PM -0700, Andy Peters wrote:
>> On Jul 14, 2007, at 11:48 AM, Steve Meier wrote:
>>
>>> This is an area that writting some code could be very usefull. How
>>> about
>>> a limited auto router that takes the bga io tra
On Jul 15, 2007, at 9:01 AM, Stephen Williams wrote:
> DJ Delorie wrote:
>
>> In theory, via-in-pad lets you bring an extra row out on the top
>> layer. It might mean the difference between 12 and 14 layers.
>
> Also, if you avoid masking the bottom side of the via, you suddenly
> have scope acce
Looks like i need a remedial course in elementary school math.
make the pads 17 mills (.43 mm) then you have 5.2 mills between the
copper traces and the pads.
Steve M.
Steve Meier wrote:
> Harold,
>
> Try this geometry. 1 mm pitch is ~39.4 mills
>
> Make the 2 traces 4 mills make the spacing bet
DJ Delorie wrote:
> In theory, via-in-pad lets you bring an extra row out on the top
> layer. It might mean the difference between 12 and 14 layers.
Also, if you avoid masking the bottom side of the via, you suddenly
have scope access to every pad of the BGA, which I've found to be
amazingly use
> Putting a via in pad isn't necessary you can put the via between
> pads and then run your traces under the pads. The via in pad just
> gives you better usage of the surface that your device is mounted
> to.
In theory, via-in-pad lets you bring an extra row out on the top
layer. It might mean t
Putting a via in pad isn't necessary you can put the via between pads
and then run your traces under the pads. The via in pad just gives you
better usage of the surface that your device is mounted to.
Steve Meier
Harold D. Skank wrote:
> Steve,
>
> Sorry about that. I checked the Xilinx footprin
Harold,
Try this geometry. 1 mm pitch is ~39.4 mills
Make the 2 traces 4 mills make the spacing between the traces 4 mills.
make your pads 18 mills diameter.
this leaves you 5.5 mills from the edge of a trace to a pad.
Check with your fab shop I will bet they can do it using 1/2 oz copper.
5.
Steve,
Sorry about that. I checked the Xilinx footprint info and you're
correct, the spacing is 1 mm. Even so, the problem doesn't change, as
we have to use drilled pads, backfilled with epoxy. By the time you've
accounted for the sufficient pad size for chip attachment and accounted
for a 5 mi
0.5mm is 20 mil pitch, there's no way you're getting two traces out
unless you've got 2/2 rules and 10 mil pads.
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If you have 25 mils of open space between pads then you can route two 5
mill width traces with 5 mills of clearence on either side and between
which meets the design requirements of my usual fab shop.
Steve M.
Steve Meier wrote:
> Harold,
>
> Can you check that again. 45 mills is 1.143 mm.
>
> Th
On Sat, Jul 14, 2007 at 04:43:38PM -0700, Andy Peters wrote:
> On Jul 14, 2007, at 11:48 AM, Steve Meier wrote:
>
> > This is an area that writting some code could be very usefull. How
> > about
> > a limited auto router that takes the bga io traces out just past the
> > nearest edge?
>
> A "fa
On Jul 14, 2007, at 11:48 AM, Steve Meier wrote:
> Hmmm,
>
> This is an area that writting some code could be very usefull. How
> about
> a limited auto router that takes the bga io traces out just past the
> nearest edge?
A "fanout" command, like what DXP and others have, is VERY useful.
-a
Harold,
Can you check that again. 45 mills is 1.143 mm.
Thanks,
Steve Meier
On Sat, 2007-07-14 at 15:43 -0500, Harold D. Skank wrote:
> Steve,
>
> You're pretty much right about every thing except the pin density.
> We're using Vertex 5, with pins spaced at 0.5 mm, pin to pin. This
> limits t
Steve,
You're pretty much right about every thing except the pin density.
We're using Vertex 5, with pins spaced at 0.5 mm, pin to pin. This
limits the routing out from each pin to essentially 1 trace between
pins.
Harold
On Sat, 2007-07-14 at 08:19 -0700, Steve Meier wrote:
> I think it is
Hmmm,
This is an area that writting some code could be very usefull. How about
a limited auto router that takes the bga io traces out just past the
nearest edge?
Steve Meier
On Sat, 2007-07-14 at 11:41 -0700, Steve Meier wrote:
> Ben,
>
> I think you have the correct idea.
>
> I would hand r
Ben,
I think you have the correct idea.
I would hand route the traces from under the fpga and perhaps around the
other major periferal chips. Then i would sort out the rats nest by
swapping io pins. After that I would let the autorouter take a shot at
the layout.
As a explination/warning about t
How about a picture from the past?
This was a 900 pin fpga where I used via in pad.
http://www.alchemyresearch.com/bga.jpg
Steve Meier
On Sat, 2007-07-14 at 10:41 -0700, Ben Jackson wrote:
> On Sat, Jul 14, 2007 at 08:19:34AM -0700, Steve Meier wrote:
> >
> > p.s. my current project uses 1020
On Sat, Jul 14, 2007 at 08:19:34AM -0700, Steve Meier wrote:
>
> p.s. my current project uses 1020 pin fpgas and was layed out on 12
> layers. One key is to be willing to swap io pins at layout time to
> minimize the need for traces to cross each other.
It would be great if someone doing advanced
I think it is the use of the autorouter then that is driving your need
for layers.
1700 pins is what an array of 42 by 42 with a 1 millimeter spacing? You
should be able to get two traces per layer in between each pair of balls.
How many IO lines are you using? xilinx vertext 3 with 1760 pads ha
Mr. Jackson,
I VERY MUCH appreciate your response and comments. In answer to your
question, "yes, I will use a 24-layer PCB if it's fully necessary."
This issue arises because the principal chip in the circuit has
something like 1700 pins and uses 3 to 4 different voltages on something
like a 45
On Fri, Jul 13, 2007 at 07:40:12PM -0500, Harold D. Skank wrote:
>
> I'm on a critical job, pretty large, sufficient that I had to recompile
> for 24 route layers. Following the re-compile, I seem to be OK for
> everything until I attempt to start a route, at which point I get the
> "stale ratsne
People,
I'm dying here.
I'm on a critical job, pretty large, sufficient that I had to recompile
for 24 route layers. Following the re-compile, I seem to be OK for
everything until I attempt to start a route, at which point I get the
"stale ratsnest" message.
I've delt with this message before,
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