On 1 May 2007, at 11:15:09 AM, Stephen Williams wrote:
This is a bit too glib for my tastes. Parameters, parameter overrides
and constraints on parameters were thoroughly debated during the
standardization process, so I don't think it's quite fair for you
to assume you know so much more (or are
[EMAIL PROTECTED] wrote:
> In any case, as I stated in my last email,
> this feature probably isn't good to add,
> strictly because it seems to be nonstandard.
>
> However, the lack of such a feature shows
> the poor thought of Verilog's designers.
>
> The burden is on the programmer, not
> the t
[EMAIL PROTECTED] wrote:
However, the lack of such a feature shows
the poor thought of Verilog's designers.
Sssh they're out there somewhere, and they may be listening.
The burden is on the programmer, not
the tools.
The main problem with both Verilog and VHDL is that they're both
ea
On 1 May 2007, at 4:02:28 AM, Evan Lavelle wrote:
Stephen Williams wrote:
[EMAIL PROTECTED] wrote:
Basically, I'm whining for a feature.
I've looked at the thread in comp.lang.verilog. The parameter
definition circularity problem is nasty, but a carefully contained
extension (a la the way Mo
Stephen Williams wrote:
[EMAIL PROTECTED] wrote:
Basically, I'm whining for a feature.
I've looked at the thread in comp.lang.verilog. The parameter
definition circularity problem is nasty, but a carefully contained
extension (a la the way Modelsim handles it) seems plausible.
This is a good
On 30 Apr 2007, at 10:20:13 PM, Stephen Williams wrote:
I've looked at the thread in comp.lang.verilog. The parameter
definition circularity problem is nasty, but a carefully contained
extension (a la the way Modelsim handles it) seems plausible.
This is a good candidate for the Feature Request
[EMAIL PROTECTED] wrote:
> module A (input theInput, output theOutput);
> parameter delay = 2;
>
> // Do something
>
> endmodule
>
> module B (input theInput, output theOutput);
> parameter delay = a.delay + 5;
>
> A a(theInput, theOutput);
>
>
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